Abstract: A method and apparatus are disclosed in which defect behavior in an integrated circuit is discovered and modeled rather than assuming defect behavior in the form of a fault. A plurality of tests are performed on an integrated circuit to produce passing and failing responses. The failing responses are examined in conjunction with circuit description data to identify fault locations. For at least certain of the fault locations, the logic-level conditions at neighboring locations which describe the behavior of a failing response are identified. Those logic level conditions are combined into a macrofault for that location. The macrofault is then validated and can be then used to identify more tests for further refining the diagnosis. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

Abstract: A method and apparatus are disclosed in which defect behavior in an integrated circuit is discovered and modeled rather than assuming defect behavior in the form of a fault. A plurality of tests are performed on an integrated circuit to produce passing and failing responses. The failing responses are examined in conjunction with circuit description data to identify fault locations. For at least certain of the fault locations, the logic-level conditions at neighboring locations which describe the behavior of a failing response are identified. Those logic level conditions are combined into a macrofault for that location. The macrofault is then validated and can be then used to identify more tests for further refining the diagnosis. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

Abstract: A method to describe a circuit pattern comprises identifying vertices and those edges of the circuit pattern that are not incident with any vertex contained within a region of interest within the circuit pattern. The region of interest includes a portion of a polygon that is less than the entire polygon. The vertices and edges of the circuit pattern are compared to a predetermined set of known vertices and edges. A match may be used to identify an acceptable circuit or a defective circuit.

Abstract: A method to describe a circuit pattern comprises identifying vertices and those edges of the circuit pattern that are not incident with any vertex contained within a region of interest within the circuit pattern. The region of interest includes a portion of a polygon that is less than the entire polygon. The vertices and edges of the circuit pattern are compared to a predetermined set of known vertices and edges. A match may be used to identify an acceptable circuit or a defective circuit.

Abstract: A method of using static power supply current in response to test vectors for acceptance testing and defect diagnosis of CMOS integrated circuit die. Testing is based on comparison of two or more power supply current measurements from the die under test. Defect diagnosis is based on characterizing a defect by one or more current levels produced by the circuit in the presence of the defect.

Abstract: An integrated circuit function unit operating in a data dependent manner in logic operations of variable lengths of time is provided with a clock signal having a pulse width determined by the active period of the function unit. In one embodiment a current sensor monitors power supply current to the integrated circuit, and when the current exceeds a threshold level the integrated circuit is in an active period. Clock means for generating a clock signal for the function unit responds to the sensed current in controlling the clock period.

Abstract: A floating gate NMOS enhancement mode transistor is utilized in an NMOS SRAM thereby reducing power consumption, size, and circuit complexity of the memory cell. The gate of the load transistor is allowed to float with no galvanic connection to the memory cell circuit. A bias voltage is induced on the gate of the load transistor by capacitances of the gate with the source, the drain, and the bulk semiconductor, and the conductance is maintained below conduction threshold. Gate bias is established by tailoring of the gate capacitances and by the removal of charge using UV light as necessary.

Abstract: Vertically propagated defects in integrated circuits are detected utilizing an apparatus which includes a first meander structure formed on or in a substrate and a second meander structure electrically insulated from the first meander. Each meander includes intermediate segments, the ends of which are interconnected by folded segments. A first set metal of strips are electrically insulated from the first and second meanders. The ends of each strip in the first set are electrically connected to the ends of a corresponding intermediate segment of the first meander. A second set metal or strips are electrically insulated from the first set of strips, the first meander and the second meander. The ends of each strip in the second set are electrically connected to the ends of a corresponding intermediate segment of the second meander and at least a portion of the second set of strips overlies at least a portion of the first set of strips.

Abstract: Spot defects are detected utilizing an apparatus which comprises a meander structure formed in a high resistivity material on a substrate. The meandor includes intermediate segments, the ends of which are interconnected by folded segments such that an electrical circuit having electrical resistance R is formed between the ends of the meander. A strip of high electrical conductivity material is formed in substantial alignment with and is electrically insulated from a corresponding one of each of the intermediate segments. Each end of each strip is electrically connected to a corresponding end of a corresponding intermediate segment. Defects are identified by measuring the resistance R, between the ends of the meander. This measured value is then compared to the calculated value of R. If the value of the measured resistance is substantially smaller than the calculated value, a flaw due to a spot of additional high conductivity material, is considered to be present.