Patents by Inventor Wojciech P. Maly
Wojciech P. Maly has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9640653Abstract: A semiconductor device, comprising a first semiconductor portion having a first end, a second end, and a slit portion, wherein the width of the slit portion is less than the width of at least one of the first end and the second end; a second portion that is a different material than the first semiconductor portion, a third portion that is a different material than the first semiconductor portion, wherein the second and third portions are on opposite sides of the slit portion, and at least three terminals selected from a group consisting of a first terminal connected to the first end, a second terminal connected to the second end, a third terminal connected to the second portion, and a fourth terminal connected to the third portion.Type: GrantFiled: July 30, 2012Date of Patent: May 2, 2017Assignee: Carnegie Mellon UniversityInventor: Wojciech P. Maly
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Patent number: 9153689Abstract: A semiconductor device (10), comprising a first semiconductor portion (32) having a first end (34), a second end (36), and a slit portion (30), wherein the width of the slit portion (30) is less than the width of at least one of the first end (34) and the second end (36); a second portion (38) that is a different material than the first semiconductor portion (32), a third portion (40) that is a different material than the first semiconductor portion (32), wherein the second (38) and third (40) portions are on opposite sides of the slit portion (30), and at least three terminals selected from a group consisting of a first terminal (12) connected to the first end (34), a second terminal (14) connected to the second end (36), a third terminal (16) connected to the second portion (38), and a fourth terminal (17) connected to the third portion (40).Type: GrantFiled: December 13, 2011Date of Patent: October 6, 2015Assignee: Carnegie Mellon UniversityInventor: Wojciech P. Maly
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Publication number: 20130154010Abstract: A semiconductor device, comprising a first semiconductor portion having a first end, a second end, and a slit portion, wherein the width of the slit portion is less than the width of at least one of the first end and the second end; a second portion that is a different material than the first semiconductor portion, a third portion that is a different material than the first semiconductor portion, wherein the second and third portions are on opposite sides of the slit portion, and at least three terminals selected from a group consisting of a first terminal connected to the first end, a second terminal connected to the second end, a third terminal connected to the second portion, and a fourth terminal connected to the third portion.Type: ApplicationFiled: July 30, 2012Publication date: June 20, 2013Applicant: CARNEGIE MELLON UNIVERSITYInventor: Wojciech P. Maly
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Patent number: 8259286Abstract: An apparatus for forming an energy pattern on a target, comprising a projector including a first row of spaced-apart energy outlets arranged in a first pattern, a second row of spaced apart energy outlets arranged in a second pattern, wherein the first pattern is different than the second pattern, and comprising a platform on which the target can be mounted, a motor and a controller. A method of forming a pattern in a layer of energy-sensitive material, comprising projecting a first energy pattern onto the energy-sensitive material, moving the first energy pattern relative to the layer of energy-sensitive material, projecting a second energy pattern onto the energy-sensitive material, wherein the second energy pattern is different than the first energy pattern, and moving the second energy pattern relative to the layer of energy-sensitive material.Type: GrantFiled: December 21, 2005Date of Patent: September 4, 2012Assignee: Carnegie Mellon UniversityInventor: Wojciech P. Maly
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Publication number: 20120112325Abstract: A semiconductor device (10), comprising a first semiconductor portion (32) having a first end (34), a second end (36), and a slit portion (30), wherein the width of the slit portion (30) is less than the width of at least one of the first end (34) and the second end (36); a second portion (38) that is a different material than the first semiconductor portion (32), a third portion (40) that is a different material than the first semiconductor portion (32), wherein the second (38) and third (40) portions are on opposite sides of the slit portion (30), and at least three terminals selected from a group consisting of a first terminal (12) connected to the first end (34), a second terminal (14) connected to the second end (36), a third terminal (16) connected to the second portion (38), and a fourth terminal (17) connected to the third portion (40).Type: ApplicationFiled: December 13, 2011Publication date: May 10, 2012Applicant: CARNEGIE MELLON UNIVERSITYInventor: Wojciech P. Maly
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Publication number: 20090321830Abstract: A semiconductor device, comprising a first semiconductor portion having a first end, a second end, and a slit portion, wherein the width of the slit portion is less than the width of at least one of the first end and the second end; a second portion that is a different material than the first semiconductor portion, a third portions that is a different material than the first semiconductor portion, wherein the second and third portions are on opposite sides of the slit portion, and at least three terminals selected from a group consisting of a first terminal connected to the first end, a second terminal connected to the second end, a third terminal connected to the second portion, and a fourth terminal connected to the third portion.Type: ApplicationFiled: May 15, 2007Publication date: December 31, 2009Applicant: Carnegie Mellon UniversityInventor: Wojciech P. Maly
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Publication number: 20080137051Abstract: An apparatus for forming an energy pattern on a target, comprising a projector including a first row of spaced-apart energy outlets arranged in a first pattern, a second row of spaced apart energy outlets arranged in a second pattern, wherein the first pattern is different than the second pattern, and comprising a platform on which the target can be mounted, a motor and a controller. A method of forming a pattern in a layer of energy-sensitive material, comprising projecting a first energy pattern onto the energy-sensitive material, moving the first energy pattern relative to the layer of energy-sensitive material, projecting a second energy pattern onto the energy-sensitive material, wherein the second energy pattern is different than the first energy pattern, and moving the second energy pattern relative to the layer of energy-sensitive material.Type: ApplicationFiled: December 21, 2005Publication date: June 12, 2008Applicant: CARNEGIE MELLON UNIVERSITYInventor: Wojciech P. Maly
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Patent number: 5528604Abstract: Test pattern generation for a sequential logic circuit having combinational logic elements and sequential elements (D flip-flops) is enhanced in generation time and test pattern quality by first transforming the circuit to simplify the circuit for test pattern generation. In one embodiment the retiming transformation is used in which sequential elements are moved across combinational logic elements to increase the ratio of the total number of states which are traversable, and thus simplify the circuit for test pattern generation. The test set generated is equally applicable to the transformed test circuit as well as the manufactured circuit.Type: GrantFiled: January 18, 1995Date of Patent: June 18, 1996Assignee: Carnegie Mellon UniversityInventors: Aiman H. El-Maleh, Wojciech P. Maly, Thomas E. Marchok, Janusz E. Rajski
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Patent number: 5025344Abstract: A built in current sensor on a unitary substrate with an integrated circuit is provided to sense abnormal quiescent current flow through the integrated circuit after a timing phase as an indication of defects such as shorts and open circuits, while ignoring normal high current peaks. A comparator is provided along with an adjustable reference current to provide a virtual ground voltage which represents that induced by a normal quiescent current through a fault-free integrated circuit. A breaker circuit may be provided for indication, or power disconnection of the integrated circuit, upon the occurrence of current flow above a predetermined value.Type: GrantFiled: February 22, 1990Date of Patent: June 18, 1991Assignee: Carnegie Mellon UniversityInventors: Wojciech P. Maly, Phillip J. Nigh