Patents by Inventor Wolf Witt
Wolf Witt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240004808Abstract: Embodiments described herein may include apparatus, systems, techniques, or processes that are directed prioritizing memory requests from core processors such that some memory transaction requests receive a higher priority than other memory transaction requests. In some embodiments, queue lengths and latency, frequency of core demand transaction prioritization and the like are monitored and prioritization throttled accordingly. Other embodiments may be described and/or claimed.Type: ApplicationFiled: June 30, 2022Publication date: January 4, 2024Inventors: Sai Prashanth Muralidhara, Narasimha Sridhar Srirangam, Rawan Abdel Khalek, Yedidya Hilewitz, Daniel Liu, Sharada Venkateswaran, Wolf Witt, Nishant Singh
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Patent number: 8725787Abstract: A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.Type: GrantFiled: April 26, 2012Date of Patent: May 13, 2014Assignee: Intel CorporationInventors: Alexander D. Peleg, Millind Mittal, Larry M. Mennemeier, Benny Eitan, Carole Dulong, Eiichi Kowashi, Wolf Witt
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Publication number: 20120331028Abstract: A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.Type: ApplicationFiled: September 4, 2012Publication date: December 27, 2012Inventors: Alexander D. Peleg, Millind Mittal, Larry M. Mennemeier, Benny Eitan, Carole Dulong, Eiichi Kowashi, Wolf Witt
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Publication number: 20120216018Abstract: A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.Type: ApplicationFiled: April 26, 2012Publication date: August 23, 2012Inventors: Alexander D. Peleg, Millind Mittal, Larry M. Mennemeier, Benny Eitan, Carole Dulong, Eiichi Kowashi, Wolf Witt
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Patent number: 8185571Abstract: A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.Type: GrantFiled: March 23, 2009Date of Patent: May 22, 2012Assignee: Intel CorporationInventors: Alexander D. Peleg, Millind Mittal, Larry M. Mennemeier, Benny Eitan, Carole Dulong, Eiichi Kowashi, Wolf Witt
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Publication number: 20110264895Abstract: A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.Type: ApplicationFiled: July 1, 2011Publication date: October 27, 2011Inventors: Alexander D. Peleg, Millind Mittal, Larry M. Mennemeier, Benny Eitan, Carole Dulong, Eiichi Kowashi, Wolf Witt
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Publication number: 20090265409Abstract: A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.Type: ApplicationFiled: March 23, 2009Publication date: October 22, 2009Inventors: Alexander D. Peleg, Millind Mittal, Larry M. Mennemeier, Benny Eitan, Carole Dulong, Eiichi Kowashi, Wolf Witt
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Patent number: 7509367Abstract: A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.Type: GrantFiled: June 4, 2004Date of Patent: March 24, 2009Assignee: Intel CorporationInventors: Alexander D. Peleg, Millind Mittal, Larry M. Mennemeier, Benny Eitan, Carole Dulong, Eiichi Kowashi, Wolf Witt
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Patent number: 7424505Abstract: A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.Type: GrantFiled: November 19, 2001Date of Patent: September 9, 2008Assignee: Intel CorporationInventors: Alexander D. Peleg, Millind Mittal, Larry M. Mennemeier, Benny Eitan, Carole Dulong, Eiichi Kowashi, Wolf Witt
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Patent number: 7395298Abstract: A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.Type: GrantFiled: June 30, 2003Date of Patent: July 1, 2008Assignee: Intel CorporationInventors: Eric Debes, William W. Macy, Jonathan J. Tyler, Alexander D. Peleg, Millind Mittal, Larry M. Mennemeier, Benny Eitan, Carole Dulong, Eiichi Kowashi, Wolf Witt
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Publication number: 20040220992Abstract: A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.Type: ApplicationFiled: June 4, 2004Publication date: November 4, 2004Inventors: Alexander D. Peleg, Millind Mittal, Larry M. Mennemeier, Benny Eitan, Carole Dulong, Eiichi Kowashi, Wolf Witt
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Publication number: 20040117422Abstract: A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.Type: ApplicationFiled: June 30, 2003Publication date: June 17, 2004Inventors: Eric Debes, William W. Macy, Jonathan J. Tyler, Alexander D. Peleg, Millind Mittal, Larry M. Mennemeier, Benny Eitan, Carole Dulong, Eiichi Kowashi, Wolf Witt
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Publication number: 20020059355Abstract: A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.Type: ApplicationFiled: November 19, 2001Publication date: May 16, 2002Applicant: Intel CorporationInventors: Alexander D. Peleg, Millind Mittal, Larry M. Mennemeier, Benny Eitan, Carole Dulong, Eiichi Kowashi, Wolf Witt
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Patent number: 6385634Abstract: A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.Type: GrantFiled: August 31, 1995Date of Patent: May 7, 2002Assignee: Intel CorporationInventors: Alexander D. Peleg, Millind Mittal, Larry M. Mennemeier, Benny Eitan, Carole Dulong, Eiichi Kowashi, Wolf Witt
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Patent number: 6035316Abstract: A processor having a first and second storage having a first and second packed data, respectively. Each packed data includes a first, second, third, and fourth data element. A multiply-add circuit is coupled to the first and second storage areas. The multiply-add circuit includes a first, second, third, and fourth multiplier, wherein each of the multipliers receives a corresponding set of said data elements. The multiply-add circuit further includes a first adder coupled to the first and second multipliers, and second adder coupled to the third and fourth multipliers. A third storage area is coupled to the adders. The third storage area includes a first and second field for saving output of the first and second adders, respectively, as first and second data elements of a third packed data.Type: GrantFiled: February 23, 1996Date of Patent: March 7, 2000Assignee: Intel CorporationInventors: Alexander D. Peleg, Millind Mittal, Larry M. Mennemeier, Benny Eitan, Carole Dulong, Eiichi Kowashi, Wolf Witt, Derrick Chu Lin, Ahmet Bindal
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Patent number: 5983256Abstract: A method and apparatus for including in a processor instructions for performing multiply-add operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least two of the data elements in this third packed data storing the result of performing multiply-add operations on data elements in the first and second packed data.Type: GrantFiled: October 29, 1997Date of Patent: November 9, 1999Assignee: Intel CorporationInventors: Alexander Peleg, Millind Mittal, Larry M. Mennemeier, Benny Eitan, Carole Dulong, Eiichi Kowashi, Wolf Witt
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Patent number: 5935240Abstract: A method for transferring packed data including the steps of first receiving an instruction from a set of instructions for transferring packed data between an extended register file and either an integer register file or a memory. In one embodiment, the extended register file includes eight registers, with each of the extended register storing up to sixty-four data bits. The integer register file also includes eight registers. The instruction includes an opcode that specifies a direction of the transfer with respect to the extended register file. The instructions are encoded in an instruction format having up to three bits addressing a destination operand and up to three bits addressing a source operand. The instruction is then translated to determine a direction of the transfer, a size of said packed data to be transferred, the address of the destination operand, and the address of the source operand.Type: GrantFiled: December 15, 1995Date of Patent: August 10, 1999Assignee: Intel CorporationInventors: Larry M. Mennemeier, Alexander D. Peleg, Andrew F. Glew, Carole Dulong, Eiichi Kowashi, Millind Mittal, Wolf Witt, Benny Eitan
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Patent number: 5859997Abstract: A method and apparatus for including in a processor instructions for performing multiply-subtract operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least one of the data elements in this third packed data storing the result of performing a multiply-subtract operation on data elements in the first and second packed data.Type: GrantFiled: August 20, 1996Date of Patent: January 12, 1999Assignee: Intel CorporationInventors: Alexander Peleg, Millind Mittal, Larry M. Mennemeier, Benny Eitan, Wolf Witt, Carole Dulong, Eiichi Kowashi
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Patent number: 5721892Abstract: A method and apparatus for including in a processor instructions for performing multiply-subtract operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least one of the data elements in this third packed data storing the result of performing a multiply-subtract operation on data elements in the first and second packed data.Type: GrantFiled: November 6, 1995Date of Patent: February 24, 1998Assignee: Intel CorporationInventors: Alexander Peleg, Millind Mittal, Larry M. Mennemeier, Benny Eitan, Wolf Witt, Carole Dulong, Eiichi Kowashi