Abstract: In a receiver, a frequency-synthesis circuit (SYNTH) generates a stepped-frequency signal (Ssf) having a frequency which can be varied in steps. A synchronization circuit (LOOP) synchronizes a tuning oscillator (LO) with the stepped-frequency signal (Ssf). It provides an integer frequency-relationship between the stepped-frequency signal (Ssf) and the tuning oscillator (LO). That is, if the stepped-frequency signal (Ssf) has a frequency Fsf, the tuning oscillator (LO) will operate at a frequency Flo=N·Fsf, N being an integer or an integer fraction.

Abstract: In a receiver, a frequency-synthesis circuit (SYNTH) generates a stepped-frequency signal (Ssf) having a frequency which can be varied in steps. A synchronization circuit (LOOP) synchronizes a tuning oscillator (LO) with the stepped-frequency signal (Ssf). It provides an integer frequency-relationship between the stepped-frequency signal (Ssf) and the tuning oscillator (LO). That is, if the stepped-frequency signal (Ssf) has a frequency Fsf, the tuning oscillator (LO) will operate at a frequency Flo=N·Fsf, N being an integer or an integer fraction.

Abstract: In a receiver, a frequency-synthesis circuit (SYNTH) generates a stepped-frequency signal (Ssf) having a frequency which can be varied in steps. A synchronization circuit (LOOP) synchronizes a tuning oscillator (LO) with the stepped-frequency signal (Ssf). It provides an integer frequency-relationship between the stepped-frequency signal (Ssf) and the tuning oscillator (LO). That is, if the stepped-frequency signal (Ssf) has a frequency Fsf, the tuning oscillator (LO) will operate at a frequency Flo=N·Fsf, N being an integer or an integer fraction.

Abstract: Frequency synthesizers are used for down conversion of RF signals in a lot of applications, such as digital and analog radio and television receivers, car radios, etc. By combining the voltage-controlled oscillator of the phase-locked loop demodulator with the voltage-controlled oscillator of the frequency synthesizer, a major cost reduction can be achieved, but measures have to be taken to prevent that the two PLLs try to lock the same VCO to different frequencies. These measures include providing a switching circuit between the phase frequency comparator and the charging circuit, and controlling the switching circuit by using a frequency window detector.

Abstract: An interference detection circuit includes a circuit, in particular a non-linear circuit, for defining a discrimination curve in terms of instantaneous magnitude and instantaneous frequency, and a circuit, in particular a differential amplifier, for detecting whether a combination, in particular the product, of the instantaneous magnitude and the instantaneous frequency of the inputted signal exceeds the discrimination curve, in which case, a control circuit controls the gating of the inputted signal. The discrimination defining circuit has a control input for adapting the discrimination curve to the average instantaneous magnitude, in particular, the product of the instantaneous magnitude and the instantaneous frequency of the input signal. Thus, small as well as larger input signal amplitudes on which interference is superimposed can be discriminated adequately and reliably in order to minimize audible effects of leaving out interfered part of the input signal.

Abstract: A charge pump (CP) is provides for supplying at its output (23) a first current in response to an up-pulse and sinking a second current in response to a down pulse. This charge pump includes a first circuit 200, 22, CM1) for converting the first control signal into the first current, and a second circuit (206, 208, CM2) for converting the second control signal into the second current, said the first and second circuits include circuitry means comprising means (CM1, CM2) for filtering the respective control signals. It is recognized that a charge pump does not have to supply or sink current pulses which are rectangularly shaped in order for it to properly carry out its function. In the subject charge pump invention, the current sources supply or sink current pulses are smoothly shaped because the control signals supplied to the current sources are filtered. This causes the demands on the high frequency performance of the current sources to be greatly reduced.

Abstract: A logarithmic level detector that provides a very accurate level detector output signal that is greatly insensitive to temperature and process spread. The logarithmic level detector includes a weighted summed reference circuit which is subtracted from a level output signal of the cascade of limiting amplifiers so as to form a relative level detector output signal, and further compensation circuitry at input and output side, and an overall gain stabilizing circuit.

Abstract: A receiver, an arrangement and a method for comparing two signals, based on testing whether a first signal exhibits at least one property during a first time interval, and consecutively testing if a second signal exhibits at least one similar property during a second time interval, following the first time interval, the second time interval being in the range of 200 us to 5 ms. The assumption is made that if a first signal exhibits a certain property during a first time interval, it is likely to exhibit substantially the same property during a second time interval, following the first interval. Thus, if a second signal exhibits such a property during the second time interval, the second signal is deemed to be the same as the first signal. If both tests are positive, the two signals are determined to be the same. In this way, both signals need not be present simultaneously.

Abstract: An FM receiver having an RF section, a first tunable mixer stage for the frequency conversion of a desired RF FM reception signal into a first intermediate frequency signal, an IF device and an FM demodulator. In order to enhance the integration of the apparatus, while maintaining a signal processing ability which is free from distortion, the FM receiver includes circuitry incorporated in the signal path for converting a single-phase signal into a pair of signals in mutual phase quadrature. The pair of phase-quadrature signals is applied to in-phase and quadrature signal paths of the IF device. The IF device having a polyphase IF filter incorporated in the in-phase and quadrature signal paths and has a bandpass characteristic which is symmetrical around its resonance frequency. The polyphase IF filter is coupled to the FM demodulator.

Abstract: An FM demodulator having two input terminals (11, 12), to which FM input signals having 90.degree. phase relation are applied, the said FM demodulator including a phase comparator (1) and a tunable, phase shifting circuit (2), the phase shifting circuit (2) being tuned by the FM demodulator output signal via a feedback path comprising a loop, filter. By adding a compensation filter (5) to the tuning control loop the phase shifting circuit is effectively cancelled from the tuning control loop, thereby making the tuning control loop independent of the bandwidth of the phase shifting circuit (2). Thus the bandwidth of the phase shifting circuit (2) can be reduced for threshold extension.

Abstract: An FM receiver includes an RF section, a first mixer stage for converting a desired RF reception signal into a first IF signal having a carrier frequency located on average at a first intermediate frequency, a first IF section for selecting the first IF signal, and a second mixer stage for converting the first IF signal into a second IF signal having a carrier frequency located on average at a second intermediate frequency. The second intermediate frequency is below the first intermediate frequency. A second IF section selects the second IF signal and is coupled to an FM demodulator for demodulating the baseband modulation signal of the desired RF reception signal, followed by a low-pass filter for selecting the baseband modulation signal.

Abstract: An adjustable resistance device having a first parallel arrangement (1) of a first resistor and a first positive-feedback transconductor is provided with a control circuit (20) for controlling the controllable resistance section in the first parallel arrangement (1), which control circuit (20) includes a control loop including a second parallel arrangement (2) which is a copy of the first parallel arrangement (1). The control circuit (20) controls the controllable section of the second parallel arrangement (2) in such a manner that the negative resistance value formed by a second transconductor is substantially equal in magnitude to the resistance value of a second resistor, so that the second parallel arrangement (2) is bistable in the transition range.

Abstract: FM quadrature demodulator having in-phase and quadrature terminals for applying a pair of FM-modulated signals in a mutual phase quadrature thereto, having a modulation signal which is frequency-modulated on a carrier, one of the two terminals being coupled to a first input of a first phase comparison circuit and the other terminal being coupled to a second input of the first phase comparison circuit via a first phase-shifting circuit which realizes a phase shift varying with said modulation signal, the first phase comparison circuit being connected to an output of the FM quadrature demodulator via a low-pass filter.

Abstract: A receiver having an RF section, a mixer stage and a signal processing stage, the mixer stage receiving a mixing frequency from a frequency synthesis circuit which includes a phase-locked loop provided with a phase detection device having a current output, a loop filter including a .pi.-shaped RC network having an input shunt path and an output shunt path which are connected to respective ends of a series resistor incorporated in a series path, and to ground, and include first and second capacitances, respectively, and with a voltage-controlled oscillator, a reference frequency being applied to the phase detection device.

Abstract: An amplifier with a non-regenerative DC negative feedback loop which incorporates first and second first-order low-pass RC filters, has a signal path arranged from an input to an output and a feedback path arranged from the output to the input, and has a controlled loop gain. To provide substantially even selective amplification over a comparatively large tuning control range, the signal path incorporates one of the two RC filters and the feedback path incorporates the other RC filter together with the controlled loop gain; or the signal path incorporates the two RC filters together with one part of the controlled loop gain and the feedback path incorporates the other part of the controlled loop gain.

Abstract: In a digital shift register comprising a series of substantially identical bistable circuits, a reference voltage required for the bistable circuits is generated by coupling a common node to the outputs of the bistable circuits via resistors, in such a way that the reference voltage is the means of the output voltages of the bistable circuits. Further, a method is described for the advanced presentation of information to the bistable circuits of the shift register via the reference circuit, so that the bistable circuits are changed over faster and the maximum clock frequency of the shift register is increased. By incorporating a gate circuit ahead of the shift register, a programmable frequency divider may thus be provided.

Abstract: Controllable oscillator circuit comprising a regenerative loop which incorporates a cascade circuit of first and second sections each having a controllable gain and a phase shift which is 90.degree. at the oscillation frequency, and an amplitude detection arrangement which is coupled between an output and a control input of at least one of the two sections.

Abstract: A controllable quadrature oscillator, having a pair of oscillator outputs for supplying a pair of phase quadrature oscillator signals, is a cascade circuit of two quadrature sections incorporated in a regenerative loop each contributing a 90.degree. phase shift in the regenerative state of the loop. In order to increase the frequency control range of such a controllable quadrature oscillator and to enable realization by integrated circuit technology, each quadrature section is formed of two stages in cascade arranged in a signal path between an input terminal and an output terminal for the quadrature section. One of the stages includes a first amplifier having a low-pass characteristic and the other of the stages includes a second amplifier having a low-pass characteristic and having a feedback path. The gain of at least one of the two amplifiers is controllable for controlling the frequency of the pair of phase quadrature oscillator signals.

Abstract: Phase detector having a first input for an angle-modulated input carrier to be detected, and a second input for a reference carrier having a phase shift which is dependent on the angle modulation with respect to the input carrier, the input and reference carriers being at least multiplied in the phase detector, and a frequency demodulator including such a phase detector. In order to inhibit signal distortion and notably second-order interference products in the demodulation of an angle-modulated input carrier, the phase detector according to the invention is adapted to derive an in-phase carrier A and a phase quadrature carrier B from the input carrier and to derive an in-phase carrier C and a phase quadrature carrier D from the reference carrier which has a phase which, at an average, is equal or opposite to that of the input carrier, while the phase detector is further adapted to supply from its output a signal which substantially corresponds to AC-BD.

Abstract: A pair of signal paths 3-1 and 3-2 are connected in parallel to an input 2, each composed of the respective mixing stages 4-1, 4-2, low-pass filters 5-1, 5-2 and mixing stages 6-1, 6-2. The mixing stages 4-1, 4-2 are connected to the oscillator 8 in a phase-quadrature relationship. The mixing stages 6-1, 6-2 are connected to the oscillator 9 in a phase-quadrature relationship and are both connected to a superposition circuit 7 having an output 10. For obviating the drawback of unbalance in the signal processing in the signal paths 3-1, 3-2, the receiver 1 includes a control signal arrangement 11, which is constituted by the respective further mixing stages 14, 25, low-pass filters 47, 48, and mixing stages 17, 29 for producing at the control signal outputs 22, 34 an amplitude and a phase control signal for correcting this unbalance.