Patents by Inventor Wolfgang Angermann

Wolfgang Angermann has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for fabricating field-effect transistors in integrated semiconductor circuits and integrated semiconductor circuit fabricated with a field-effect transistor of this type including a dual gate
    Patent number: 6613616
    Abstract: A method for fabricating a field-effect transistor situated within an integrated semiconductor circuit. At least two gate regions each extending between a source region and a drain region and are disposed such that they lie one above the other in a thickness direction of a substrate, thereby reducing the space requirement of the hitherto customary larger field-effect transistors in integrated semiconductor circuits.
    Type: Grant
    Filed: September 12, 2001
    Date of Patent: September 2, 2003
    Assignee: Infineon Technologies AG
    Inventors: Wolfgang Angermann, Andreas Bänisch
  • Method of fabricating an integrated circuit processed on both sides
    Publication number: 20020086506
    Abstract: A silicon wafer with a thickness of the order of magnitude of 0.8 mm is firstly processed at least partially on a first side. The unthinned silicon wafer is subsequently provided, on the second side, with a second circuit structure and a metallization structure arranged above the latter. The electrical insulation of the two circuit structures is effected solely by the intermediate undoped silicon material of the wafer. The two metallization structures are connected to an external contact-making structure.
    Type: Application
    Filed: November 13, 2001
    Publication date: July 4, 2002
    Inventors: Wolfgang Angermann, Michael Pfeiffer
  • Method for farbricating field-effect transistors in integrated semiconductor circuits and integrated semiconductor circuit fabricated with a field-effect transistor of this type
    Publication number: 20020037639
    Abstract: A method for fabricating a field-effect transistor situated within an integrated semiconductor circuit. At least two gate regions each extending between a source region and a drain region and are disposed such that they lie one above the other in a thickness direction of a substrate, thereby reducing the space requirement of the hitherto customary larger field-effect transistors in integrated semiconductor circuits.
    Type: Application
    Filed: September 12, 2001
    Publication date: March 28, 2002
    Inventors: Wolfgang Angermann, Andreas Banisch