Abstract: Systems, apparatuses, and methods for transmission failure feedback associated with a memory device are described. A memory device may detect errors in received data and transmit an indication of the error when detected. The memory device may receive data and checksum information for the data from a controller. The memory device may generate a checksum for the received data and may detect transmission errors. The memory device may transmit an indication of detected errors to the controller, and the indication may be transmitted using a line that is different than an error detection code (EDC) line. A low-speed tracking clock signal may also be transmitted by the memory device over a line different than the EDC line. The memory device may transmit a generated checksum to the controller with a time offset applied to the checksum signaled over the EDC line.

Abstract: Methods, systems, and devices for pre-distortion of multi-level signaling are described. A device may identify two multi-level signals that are to be transmitted over two transmission lines at the same time. The device may estimate the crosstalk expected to be caused by one of the multi-level signals on the other during propagation. Based on the expected crosstalk, the device may generate a signal that compensates for the expected crosstalk. In some examples, the signal may be a combination of the first signal and a cancelation signal. In some examples, once the compensated signal has been generated, it is transmitted over its respective transmission line at the same time that the other multi-level is transmitted over its respective transmission line.

Abstract: Systems, apparatuses, and methods for training procedures on reference voltages and sampling times associated with symbols communicated with a memory device are described. The training procedures may be configured to compensate for variations that may occur in different symbols of a signal. For example, an individual training operation may be performed for each reference voltage within a first unit interval. These individual training operations may allow a reference voltage of the first unit interval to be positionable independent of other reference voltages in the same unit interval or in different unit intervals. In another example, an individual training operation may be performed for the sampling time associated with a reference voltage. These individual training operations may allow a sampling time associated with a reference voltage in the first unit interval to be positionable independent of other sampling times in the same unit interval or in different unit intervals.

Abstract: Methods, systems, and devices for drive strength calibration for multi-level signaling are described. A driver may be configured to have an initial drive strength and to drive an output pin of a transmitting device toward an intermediate voltage level of a multi-level modulation scheme, where the output pin is coupled with a receiving device via a channel. The receiving device may generate, and the transmitting device may receive, a feedback signal indicating a relationship between the resulting voltage of the channel and an value for the intermediate voltage level. The transmitting device may determine and configure the driver to use an adjusted drive strength for the intermediate voltage level based on the feedback signal. The driver may be calibrated (e.g., independently) for each intermediate voltage level of the multi-level modulation scheme. Further, the driver may be calibrated for the associated channel.

Abstract: A method includes varying a number of clock characteristics of each a plurality of memory devices of a memory concurrently, determining a fitness of the memory for each variation of the number of clock characteristics, selecting a particular variation of the number of clock characteristics based on the determined fitness of the memory for the particular variation, changing a setting in each of the plurality of memory devices corresponding to the particular variation to generate an additional variation of the number of clock characteristics, and determining a fitness of the memory for the additional variation.