Abstract: A large surface display apparatus is provided with at least one display field, a control set, a first connection line, and a second connection line. The display field has LCD-modules to display changing information. In one aspect, the first connection line is a light wave conductor and the second connection line is a metallic conductor.

Abstract: The electronic counter for counting a periodic clock signal generated at a preset clock frequency (f.sub.o) includes a clock circuit generating the periodic clock signal at the preset clock frequency (f.sub.o); an adjustable frequency divider (4) having an output (8), a first input (5) and a second input (7), the first input of the frequency divider (4) being connected to the clock circuit (6) so as to receive the periodic clock signal and the second input (7) of the frequency divider being connected to receive a cycle speed signal (n), the frequency divider (4) containing means to produce a pulsed output signal at a divider output frequency (c.sub.o); a tracking circuit (T) connected to the output (8) of the frequency divider (4) to receive the pulsed output signal at the divider output frequency (c.sub.

Abstract: A device for potential-free transmission of dominant and recessive data bits in a bus system operating with bit-by-bit arbitration includes a series connection of a modulator, a galvanic separation circuit, and a demodulator. Data bits to be transmitted are scanned in the modulator at equidistant time intervals and are divided into two intermediate trains of data bits wherein the dominant bits alternate with the recessive bits. The two intermediate trains are applied to two input terminals of a galvanic separating device, and a demodulation is effected on the output side of the separating device.

Abstract: A device for controlling ignition and/or injection operations in a four-stroke internal combustion engine comprises a phase-locked loop (PLL) in which a frequency divider (14) divides the number of peaks of a triangular output waveform (w) by half the number of cylinders to produce a feedback signal which is compared in a phase comparator (10) with reference marks (BM) produced by a pulse generator associated on the engine crankshaft. The rotation of the crankshaft is thereby accurately divided into the required number of segments for the spark plugs of the individual cylinders. The speed-dependent capacitor (C.sub.n) is charged or discharged upon an increase or decrease in speed (n) by means of a follower control (18), to adjust the output frequency of the waveform (w) so that it remains in synchronism with the reference marks (BM). The phase of the output waveform (w) is corrected upon an increase or decrease in speed (n) by the follower control (18) which either multiplies the current (i.sub.

Abstract: To control the ignition timing in a multicylinder engine, the computer output signal which controls the current flow through the ignition coil for generating the spark in the first cylinder is delayed and then applied to the ignition coil controlling the spark in a subsequent cylinder. The computer output signal is delayed by passing through a shift register whose clock input is derived from a pulse generator generating a pulse for each predetermined incremental angular rotation of the crankshaft. If a single ignition coil and a distributor are used, the computer output signal and the delayed computer output signal are applied to an OR gate whose output controls a switch controlling the current through the ignition coil. When more than one ignition coil is used, the computer output signal is applied to a switch controlling the current through the first coil, the delayed computer output signal to a switch controlling the current to a second coil.

Abstract: A pulse train of a first frequency is generated, for example representative of speed of an internal combustion engine, and counted in a counter in a first counting cycle until the counter reaches a predetermined count number, the counter then being reset; a second frequency signal, for example a multiplied frequency derived from the first is then applied to the counter during a second count cycle, the counter stopping to count when current flow through the ignition coil of a predetermined level is sensed, and establishing a count number from which the counter can start counting at the next subsequent first cycle. The ON time of ignition current flow is controlled to commence at the beginning of the second count cycle, terminating at the ignition instant, as controlled by an ignition time control arrangement.

Abstract: To permit real-time counting of pulses representative of operating parameters of a moving body, for example in an internal combustion engine to control the ignition timing as a function of speed and other parameters in which, upon increase in speed of the engine, the ignition pulses follow each other rapidly and to permit sufficient current flow through the ignition coil for proper ignition, pulse sequences derived from the engine, for example as a function of speed, are converted into a higher frequency and the original pulses and the higher frequency are supplied to the counter as pulse trains so that the counter will reach the appropriate count state for which the ignition angle is to be computed at a time sufficiently in advance of the triggering of the ignition current, so that the time available for flow of ignition current will be increased, even at high engine speeds.

Abstract: A speed related signal is counted out with respect to clock pulses having a predetermined rate in a counter; if, and when the counter reaches a certain predetermined number, the number is decoded and applied as a disconnect control signal to open a switch controlling current flow through the ignition coil. The number is selected to occur only if the engine operates at a very slow speed, or is stopped, so that no reset signal will be applied to the counter. A logic stage is provided having both the output of the count decoder stage as well as of the speed related signal applied thereto to ensure that disconnection is effected only when the counter has reached the decoding number, and then to continue reliably disconnection of the ignition current.

Abstract: To control the division ratio of an input frequency applied to a loop circuit including an adder, the overflow output of which is fed back to one of its inputs, the division denominator is applied to a comparator to be compared with the overflow output of the adder to select, in accordance with the comparison in the comparator, with respect to a selected denominator number, the frequency division, so that the output of the adder will be representative of a converted frequency as selected with respect to the denominator number.

Abstract: Operating parameters, such as speed and loading of the engine are converted in electrical signals which are converted into pulse rates, to control counting of an address counter, addressing a read-only (ROM) memory in which characteristics of the engine are stored. To provide easy introduction of additional parameters such as temperature, idle condition, maximum speed, start condition, etc., the final value of an accumulator counter, the number of which at a given time controls the ignition timing, can be changed; further, to simplify the system, the speed and load signals are processed during a portion of the time between successive ignition events, the remaining portion of the time being controlled solely by one of the parameters (preferably speed), thus simplifying the circuitry by providing a transfer switch connecting for the remaining period only the selected (preferably speed) signal to the accumulator counter, the count state of which controls the ignition instant.