Abstract: To provide a synthesized tuning frequency to control the local oscillator in a superheterodyne receiver, a frequency generating circuit includes a reference oscillator which provides a reference frequency which is frequency-divided to generate a plurality of divided sub-frequencies which, with respect to the reference frequency have at least a flank which is non-coincident with respect to corresponding flanks of other frequencies. These divided frequencies are added in an adder, the addition of which is controlled in accordance with a tuning command stored in a digital memory. Preferably, the adder is a NOR-gate to which selected frequencies are connected, selected by NAND-gates in accordance with a number provided by a digital tuning control and stored in the digital memory. The synthesized frequency is then used to provide an error control signal within a control loop connected to the local oscillator.

Abstract: A fuel injection apparatus for internal combustion engines, having a digital control apparatus for producing an actuating electrical signal for the engine injection valves proportional to the engine speed and the quantity of air aspirated by the engine, and a signal correction apparatus for modulating the injection actuating pulse in accordance with other parameters of the engine, such as fuel enrichment during starting or warmup of the engine, adjustment for idle, partial load, and full load conditions, and adjustment for the air-fuel ratio for both short time variable conditions, and long time variations such as variations in barometric pressure. This correction apparatus includes auxiliary storage register, interconnected to numerical frequency converters, which produce the correction signal from the information stored in the auxiliary storage registers.CROSS REFERENCE TO RELATED APPLICATIONSU.S. Application of Rolf Daumer et al, Ser. No. 742,715, filed Nov. 17, 1976.

Abstract: A central digital memory contains data relating values of operational variables of an installation to values of a stored parameter. The central memory is addressed in parallel via input lines carrying the address of the stored data. The address is generated by selecting one of several discrete input lines leading to an address selector memory which contains preliminary addresses related to the various operational states of the installation. A portion of the preliminary address is delivered directly to the central memory whereas another portion is used to preset a counter. If the particular operational state is dependent on another parameter, for example temperature, a temperature-dependent clocking frequency is admitted to the counter and alters its contents which are then used to supplement the first portion of the address already delivered to the central memory. If no temperature dependency exists, the second portion of the address is passed on without change.