Abstract: A method for etching a layer assembly, the layer assembly including an intermediate layer sandwiched between an etch layer and a stop layer, the method including a step of etching the etch layer using a first etchant and a step of etching the intermediate layer using a second etchant. The first etchant includes a first etch selectivity of at least 5:1 with respect to the etch layer and the intermediate layer. The second etchant includes a second etch selectivity of at least 5:1 with respect to the intermediate layer and the stop layer. The first etchant being is different from the second etchant.

Abstract: One or more embodiments relate to a semiconductor device that includes: a conductive layer including a sidewall; a conductive capping layer disposed over the conductive layer and laterally extending beyond the sidewall of the conductive layer by a lateral overhang; and a conductive via in electrical contact with the conductive capping layer.

Abstract: A method for etching a layer assembly, the layer assembly including an intermediate layer sandwiched between an etch layer and a stop layer, the method including a step of etching the etch layer using a first etchant and a step of etching the intermediate layer using a second etchant. The first etchant includes a first etch selectivity of at least 5:1 with respect to the etch layer and the intermediate layer. The second etchant includes a second etch selectivity of at least 5:1 with respect to the intermediate layer and the stop layer. The first etchant being is different from the second etchant.

Abstract: One or more embodiments relate to a semiconductor device that includes: a conductive layer including a sidewall; a conductive capping layer disposed over the conductive layer and laterally extending beyond the sidewall of the conductive layer by a lateral overhang; and a conductive via in electrical contact with the conductive capping layer.

Abstract: One or more embodiments relate to a semiconductor device that includes: a conductive layer including a sidewall; a conductive capping layer disposed over the conductive layer and laterally extending beyond the sidewall of the conductive layer by a lateral overhang; and a conductive via in electrical contact with the conductive capping layer.

Abstract: One or more embodiments relate to a semiconductor device that includes: a conductive layer including a sidewall; a conductive capping layer disposed over the conductive layer and laterally extending beyond the sidewall of the conductive layer by a lateral overhang; and a conductive via in electrical contact with the conductive capping layer.

Abstract: One or more embodiments relate to a semiconductor device that includes: a conductive layer including a sidewall; a conductive capping layer disposed over the conductive layer and laterally extending beyond the sidewall of the conductive layer by a lateral overhang; and a conductive via in electrical contact with the conductive capping layer.

Abstract: A method for etching a layer assembly, the layer assembly including an intermediate layer sandwiched between an etch layer and a stop layer, the method including a step of etching the etch layer using a first etchant and a step of etching the intermediate layer using a second etchant. The first etchant includes a first etch selectivity of at least 5:1 with respect to the etch layer and the intermediate layer. The second etchant includes a second etch selectivity of at least 5:1 with respect to the intermediate layer and the stop layer. The first etchant being is different from the second etchant.

Abstract: One or more embodiments may relate to a method for making a semiconductor device, including: a method for making a semiconductor device, comprising: providing a substrate; forming a charge storage layer over the substrate; forming a control gate layer over the charge storage layer; forming a mask over the control gate layer; using the mask, etching the control gate layer and the charge storage layer; forming a select gate layer over the etched control gate layer and the etched charge storage layer; forming an additional layer over the select gate layer; etching the additional layer to form sidewall spacers over the select gate layer; and etching the select gate layer.

Abstract: One or more embodiments may relate to a method for making a semiconductor device, including: a method for making a semiconductor device, comprising: providing a substrate; forming a charge storage layer over the substrate; forming a control gate layer over the charge storage layer; forming a mask over the control gate layer; using the mask, etching the control gate layer and the charge storage layer; forming a select gate layer over the etched control gate layer and the etched charge storage layer; forming an additional layer over the select gate layer; etching the additional layer to form sidewall spacers over the select gate layer; and etching the select gate layer.

Abstract: One or more embodiments relate to a semiconductor device that includes: a conductive layer including a sidewall; a conductive capping layer disposed over the conductive layer and laterally extending beyond the sidewall of the conductive layer by a lateral overhang; and a conductive via in electrical contact with the conductive capping layer.

Abstract: A method for characterizing and simulating a CMP process, in which a substrate to be polished, in particular a semiconductor wafer, is pressed onto a polishing cloth and is rotated relative to the latter for a defined polishing time. The method includes defining a set of process parameters, in particular a compressive force and a relative rotational speed between a substrate and polishing cloth; preparing and characterizing a test substrate having test patterns with different structure densities using the defined process parameters; determining a set of model parameters for simulating the CMP process from results of the characterization of the test substrate; determining layout parameters of the substrate which is to be polished; defining a profile of demands for a CMP process result for the substrate to be polished; and simulating the CMP process in order to determine the polishing time required to satisfy the profile of demands.

Abstract: A surface of a semiconductor wafer is cleaned following a chemical mechanical polishing process. With the semiconductor wafer rotating continuously, an integrated process sequence is used to etch the surface, rinse the surface, and they dry the surface. The apparatus for cleaning the semiconductor wafer has a turntable in a process chamber for rotating the wafer, a feed for cleaning medium, and a return.

Abstract: A method for characterizing and simulating a CMP process, in which a substrate to be polished, in particular a semiconductor wafer, is pressed onto a polishing cloth and is rotated relative to the latter for a defined polishing time. The method includes defining a set of process parameters, in particular a compressive force and a relative rotational speed between a substrate and polishing cloth; preparing and characterizing a test substrate having test patterns with different structure densities using the defined process parameters; determining a set of model parameters for simulating the CMP process from results of the characterization of the test substrate; determining layout parameters of the substrate which is to be polished; defining a profile of demands for a CMP process result for the substrate to be polished; and simulating the CMP process in order to determine the polishing time required to satisfy the profile of demands.

Abstract: A surface of a semiconductor wafer is cleaned following a chemical mechanical polishing process. With the semiconductor wafer rotating continuously, an integrated process sequence is used to etch the surface, rinse the surface, and they dry the surface. The apparatus for cleaning the semiconductor wafer has a turntable in a process chamber for rotating the wafer, a feed for cleaning medium, and a return.

Abstract: The polishing device grinds or polishes semiconductor substrates. The device includes a polishing table, into which a measuring device is integrated and a through opening. A polishing cloth covers the polishing table. The polishing cloth has at least one opening formed therein which corresponds to the through opening in the polishing table. The invention also relates to a polishing cloth for use in the polishing device.