Patents by Inventor Wolfgang Diewald

Wolfgang Diewald has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230330769
    Abstract: Provided is a machining apparatus including a profile sensor unit configured to obtain shape information about a parent substrate; and a laser scan unit configured to direct a laser beam onto the parent substrate, wherein a laser beam axis of the laser beam is tilted to an exposed main surface of the parent substrate, and wherein a track of the laser beam on the parent substrate is controllable as a function of the shape information obtained from the profile sensor unit.
    Type: Application
    Filed: June 16, 2023
    Publication date: October 19, 2023
    Inventors: Ralf Rieske, Alexander Binter, Wolfgang Diewald, Bernhard Goller, Heimo Graf, Gerald Lackner, Jan Richter, Roland Rupp, Guenter Schagerl, Marko David Swoboda
  • Patent number: 11712749
    Abstract: Provided is a parent substrate that includes a central region and an edge region. The edge region surrounds the central region. A detachment layer is formed in the central region. The detachment layer extends parallel to a main surface of the parent substrate. The detachment layer includes modified substrate material. A groove is formed in the edge region. The groove laterally encloses the central region. The groove runs vertically and/or tilted to the detachment layer.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: August 1, 2023
    Assignee: Infineon Technologies AG
    Inventors: Ralf Rieske, Alexander Binter, Wolfgang Diewald, Bernhard Goller, Heimo Graf, Gerald Lackner, Jan Richter, Roland Rupp, Guenter Schagerl, Marko Swoboda
  • Publication number: 20210053148
    Abstract: Provided is a parent substrate that includes a central region and an edge region. The edge region surrounds the central region. A detachment layer is formed in the central region. The detachment layer extends parallel to a main surface of the parent substrate. The detachment layer includes modified substrate material. A groove is formed in the edge region. The groove laterally encloses the central region. The groove runs vertically and/or tilted to the detachment layer.
    Type: Application
    Filed: August 6, 2020
    Publication date: February 25, 2021
    Inventors: Ralf Rieske, Alexander Binter, Wolfgang Diewald, Bernhard Goller, Heimo Graf, Gerald Lackner, Jan Richter, Roland Rupp, Guenter Schagerl, Marko Swoboda
  • Patent number: 6764954
    Abstract: The invention relates to a method for applying adjusting marks on a semiconductor disk. A small part structure consisting a non-metal is produced in an extensive metal layer and the semiconductor disk is subsequently planed in said region with the help of chemical and mechanical polishing. The structural sizes in the metal layer and the chemical-mechanical polishing process are adjusted to each other, in such a way that the small part non-metal structure protrudes above the extensive metal layer after polishing.
    Type: Grant
    Filed: January 21, 2003
    Date of Patent: July 20, 2004
    Assignee: Infineon Technologies AG
    Inventors: Wolfgang Diewald, Klaus Mümmler
  • Publication number: 20030157779
    Abstract: The invention relates to a method for applying adjusting marks on a semiconductor disk. A small part structure consisting a non-metal is produced in an extensive metal layer and the semiconductor disk is subsequently planed in said region with the help of chemical and mechanical polishing. The structural sizes in the metal layer and the chemical-mechanical polishing process are adjusted to each other, in such a way that the small part non-metal structure protrudes above the extensive metal layer after polishing.
    Type: Application
    Filed: January 21, 2003
    Publication date: August 21, 2003
    Inventors: Wolfgang Diewald, Klaus Mummler
  • Patent number: 6277761
    Abstract: A method for fabricating stacked vias for microelectronic components. The method has a first step of providing a first patterned interconnect layer on a substrate. A first insulating layer is then applied on the first interconnect layer. A first via is formed in the first insulating layer and is in contact with the first interconnect layer. A second patterned interconnect layer is applied on the first insulating layer, leaving free a region around the first via. A second insulating layer is then deposited on the second interconnect layer and on the region left free around the first via. A second via is formed in the second insulating layer in such a way that it meets the first via directly.
    Type: Grant
    Filed: July 21, 2000
    Date of Patent: August 21, 2001
    Assignee: Siemens Aktiengesellschaft
    Inventors: Wolfgang Diewald, Detlef Weber
  • Patent number: 6257955
    Abstract: An apparatus for polishing wafers includes a polishing table with a heating device. A conduit connects a tank holding a liquid polishing agent to a distributor for feeding the liquid polishing agent to the polishing table. A heat exchanger is disposed along the conduit between the tank and the distributor for heating the liquid polishing agent. The heat exchanger is independent of said heating device. A method for heating a polishing agent is also provided.
    Type: Grant
    Filed: February 29, 2000
    Date of Patent: July 10, 2001
    Assignee: Infineon Technologies AG
    Inventors: Götz Springer, Wolfgang Diewald, Andre Richter