Abstract: Disclosed herein is a system comprising a plurality of agents that desire access to a resource; a finite amount of an internal state; a processor that is configured to enforce an arbitration mechanism to translate a quota specification for the plurality of agents according to a set of rules comprising i) all classes of service that are serviceable are served according to the quota specification; ii) if an underserviced class is not serviceable, a serviceable class continues to be granted access to the one or more resources even if the granted access leads to an increase in the underservice of a non-serviceable class; iii) as soon as the underserviced class becomes serviceable, it will in priority recuperate its accumulated disadvantage until its quota specification is reached; and iv) the internal state is updated upon reaching boundary conditions.

Abstract: Disclosed herein is a system comprising a plurality of agents that desire access to a resource; a finite amount of an internal state; a processor that is configured to enforce an arbitration mechanism to translate a quota specification for the plurality of agents according to a set of rules comprising i) all classes of service that are serviceable are served according to the quota specification; ii) if an underserviced class is not serviceable, a serviceable class continues to be granted access to the one or more resources even if the granted access leads to an increase in the underservice of a non-serviceable class; iii) as soon as the underserviced class becomes serviceable, it will in priority recuperate its accumulated disadvantage until its quota specification is reached; and iv) the internal state is updated upon reaching boundary conditions.

Abstract: Disclosed herein is a method for deadlock avoidance in a network comprising partitioning in a module, a set of virtual lanes into deadlock avoidance virtual channels; where each deadlock avoidance virtual channel comprises a plurality of virtual lanes; assigning each incoming packet at the module to one of the deadlock avoidance virtual channels, and within the deadlock avoidance virtual channel to a virtual lane whose relative index corresponds to an absolute index of the virtual lane the packet would have been assigned to if the network was not provisioned with deadlock avoidance virtual channels; and transitioning each packet as it traverses the module from one deadlock avoidance virtual channel to another deadlock avoidance virtual channel when a deadlock avoidance policy so demands it.

Abstract: A modular system for a buffer memory used for storing output queues (80a-k) of a packet switch is described. A series of memories (90) are each connected to both the input lines (10a-k) and the output lines (160a-k) of the switch. Each memory (90) is provided with a memory controller (100) connected to a latch (50) which is in turn connected to AND gates (60a-k). These AND gates (60a-k) ensure that packets are only stored in the memory (90) of the module in which the first latch (50) is set. When the memory (90) is full, the memory controller (100) resets this first latch (50) in the current module and sets the corresponding first latch (50) in the next module. The packets are then read into the memory (90) of the next module. A marker circuit (70) is used to insert in the output queues (80a-k) a marker to indicate that the next entries of the queue are to be found in the next module.

Abstract: A buffer memory for use in the output queue of a packet switching network is described. The buffer consists of two separate memories (160, 170, 260, 270) connected through a multiplexer (310) to the output of the switch. A memory access control (120, 220) processes the incoming data which arrives on only some of the input lines (130, 230) and outputs it on adjacent output lines (140, 150, 240, 250). The data is written concurrently into consecutive memory locations in one of the two memories (160, 170, 260, 270).

Abstract: In a switching system interconnecting transmission links (21-i, 23-i) on which circuit switched (CS) and packet switched (PS) information is transferred, a switch fabric (11) is provided which interconnects a plurality of input ports (15-i) to a plurality of output ports (19-i). The information arriving on incoming links is converted in switch adapters (13-i) to uniform minipackets, each having a routing address designating the required output port. The switch fabric consists of parallel equal switching slices, e.g. binary routing trees (71), which transfer in a non-blocking manner each minipacket from its input port to one output port in response to the routing address. Collecting means (73, 75) are provided at each output port for accepting the minipackets arriving from the different input ports.