Abstract: In accordance with an embodiment, a circuit arrangement includes a combinatorial circuit having a group of inputs and a group of outputs, where the combinatorial circuit is configured, during error-free operation of the combinatorial circuit, to map a codeword, present at the group of inputs, of a first error code to a codeword of a second error code at the group of outputs, and to map a non-codeword, present at the group of inputs, of the first error code to a non-codeword of the second error code; and a memory circuit configured to store an output of the combinatorial circuit at the group of outputs, and configured to correct at least 1-bit errors occurring during storage

Abstract: An apparatus employed in a processing device comprises a processor configured to process data of a predefined data structure. A memory fetch device is coupled to the processor and is configured to determine a plurality of addresses of packed data and fetch the packed data from a memory device based on the plurality of addresses. The packed data is stored on the memory device that is coupled to the processor. The memory fetch device is further configured to provide output data based on the fetched packed data to the processor, where the output data is configured according to the predefined data structure. The memory fetch device is configured to process the packed data in a predefined order.

Abstract: An apparatus employed in a processing device comprises a processor configured to process data of a predefined data structure. A memory fetch device is coupled to the processor and is configured to determine addresses of the packed data for the processor. The packed data is stored on a memory device that is coupled to the processor. The memory fetch device is further configured to provide output data based on the addresses of the packed data to the processor, where the output data is configured according to the predefine data structure.

Abstract: An apparatus employed in a processing device comprises a processor configured to process data of a predefined data structure. A memory fetch device is coupled to the processor and is configured to determine addresses of the packed data for the processor. The packed data is stored on a memory device that is coupled to the processor. The memory fetch device is further configured to provide output data based on the addresses of the packed data to the processor, where the output data is configured according to the predefine data structure.

Abstract: The invention provides a method for connecting test bench elements (102a–102f), and a shell device, a test bench element shell (201) partially or completely surrounding a circuit unit (101) to be verified, so that test bench elements (102a–102f) can be connected to the test bench element shell (201). Test data streams (203a–203f) pass in each case between the test bench elements (102a–102f) and the test bench element shell (201), the test bench element shell (201) which surrounds the circuit unit (101) to be verified being connected via interface data streams (P0(0)–P0(7), P1(0)–P1(7), 204a, 204b, 204c) to the circuit unit (101) to be verified. The test bench element shell (201) ensures that in each case a specific protocol with associated operations can be executed, during which process, depending on the configuration, an interface exchanges interface data streams (P0(0)–P0(7), P1(0)–P1(7), 204a–204c) of the circuit unit (101) to be verified with the corresponding test bench element (102a–102f).

Abstract: Method for connecting test bench elements and shell device The invention provides a method for connecting test bench elements (102a-102f), and a shell device, a test bench element shell (201) partially or completely surrounding a circuit unit (101) to be verified, so that test bench elements (102a-102f) can be connected to the test bench element shell (201). Test data streams (203a-203f) pass in each case between the test bench elements (102a-102f) and the test bench element shell (201), the test bench element shell (201) which surrounds the circuit unit (101) to be verified being connected via interface data streams (P0(0)-P0(7), P1(0)-P1(7), 204a, 204b, 204c) to the circuit unit (101) to be verified.

Abstract: In the circuit arrangement, combinatorial blocks are arranged between an input register (RG1) and an output register (RG2). The output of the input register (before the combinatorial blocks (KBL)) is connected to an analysis unit (ANA) that analyzes the value (EW) of the output of the input register (RG1) and send an enable signal (EN) to the output register (RG2) (after the combinatorial blocks) when the output value (AW) of the combinatorial blocks (KBL) must be present after the value (EW) of the output of the input register (RG1). The transit time required for an operation in the circuit arrangement can thus be shortened given certain value combinations.

Abstract: A fault search method and apparatus for simplified use and control of fault search in a system with several different models such as, for example, a hardware model, a software program and a test bench model. A user activates a uniform debugger, which, in turn, retrieves and executes various subordinate debuggers that are each allocated to a different model. The subordinate debuggers then access the different models allocated to them for the performance of corresponding fault search operations.

Abstract: Method, computer program product, programmed data medium, and computer system searches the source code of a computer program initially for infringements of prescribed consistency, syntax, grammar, and lexical rules. For an infringement of a prescribed rule, a possible correction is calculated. The source code of the computer program is then automatically or interactively changed in accordance with the calculated correction. Alternatively, it is possible to define infringements that are automatically ignored during analysis.

Abstract: A method for optimizing signal running times in a reprogrammable combinational circuit having individual cells which, in turn, contain a respective combinational block and a register. Optimization occurs after the programming of the circuit in that individual registers are reprogrammed; i.e., registers switched used are switched unused or vice versa.

Abstract: Combinatorial blocks (KBL) are arranged between an input register (RG1) and output register (RG2) in the circuit arrangement. The input (E.sub.-- RG1) and the output (A.sub.-- RG1) of the input register (RG1) connected preceding the combinatorial blocks (KBL) is connected to a comparison unit (COM) that compares the value at the input and at the output of the input register (RG1) and, given occurrence of a signal value change at the input, outputs a control signal for loading the output value of the combinatorial blocks (KBL) into the output register (RG2) connected following the combinatorial blocks. In this way, the running time required for an operation in the circuit arrangement can be shortened given specific value combinations.