Abstract: A method and apparatus relates to hardware-to-hardware data transmission in computer systems, and in particular, it relates to method and system for operating I/O adapters attaching either one or more computing devices to an I/O periphery, to a network, or to other computing devices. It is proposed to operate a memory local to the network coupling adapter as a cache memory relative to a system memory associated with the one or more computing devices for storing transmission control information.

Abstract: A method and apparatus relates to hardware-to-hardware data transmission in computer systems, and in particular, it relates to method and system for operating I/O adapters attaching either one or more computing devices to an I/O periphery, to a network, or to other computing devices. It is proposed to operate a memory local to the network coupling adapter as a cache memory relative to a system memory associated with the one or more computing devices for storing transmission control information.

Abstract: A method and apparatus relates to hardware-to-hardware data transmission in computer systems, and in particular, it relates to method and system for operating I/O adapters attaching either one or more computing devices to an I/O periphery, to a network, or to other computing devices. It is proposed to operate a memory local to the network coupling adapter as a cache memory relative to a system memory associated with the one or more computing devices for storing transmission control information.

Abstract: Method and apparatus for sending data from one partition to a second partition within a logically partitioned computer. In a data processing system having multiple logical partitions, a send queue is established in the first logical partition, and a receive queue is established in the second logical partition. The send queue is registered in the send queue in a lookup table available to all of the logical partitions. The send queue is registered using as a key the logical partition identification of the first logical partition and the subchannel number (LPAR-ID.SUBCHANNEL#) of the subchannel assigned to the partition. The receive queue is registered in the lookup table using as a key, the internet protocol address of the receive queue in the second partition. A send instruction from the first logical partition is executed which interrogates the lookup table using the LPAR-ID.

Abstract: The invention relates to a server computer comprising an adapter component (6) for receiving of a request from an operating system and having an access rights administration module (8) for assigning of access rights to the operating system and for granting of the request in case of compliance with the corresponding access rights, and a fibre channel module (14) for sending the request to the resource via a fibre channel.

Abstract: A method and apparatus relates to hardware-to-hardware data transmission in computer systems, and in particular, it relates to method and system for operating I/O adapters attaching either one or more computing devices to an I/O periphery, to a network, or to other computing devices. It is proposed to operate a memory local to the network coupling adapter as a cache memory relative to a system memory associated with the one or more computing devices for storing transmission control information.

Abstract: An Internal I/O Facility (iIOF) having a general interface for executing I/O related applications in an Input/Ouput SubSystem (IOSS) of a computer system. IIOF applications are executed in the IOSS outside the scope of CPU applications executed under the operating system (OS) of the computer system. IIOF applications are allowed to use all facilities in the IOSS. An iIOF subchannel extension is provided for those subchannels which can execute an iIOF application. IIOF subchannel extensions contain interception control fields which determine if conventional processing for the subchannel by the IOSS is to be intercepted to execute an iIOF application. A front-end interception bit in a subchannel extension is used to initiate iIOF application execution when the subchannel is taken from the IOSS work request queue. A back-end interception bit in a subchannel extension is used to initiate iIOF application execution when the subchannel is to have status put on the IOSS interruption queue.

Abstract: Highly dispersed, powdery material is fluidized in a supply container 1, falls to the diaphragm pumps 2 and/or 3 and from there is pumped via the filling tube 4 and/or 5 into the horizontal or, in a given case tilted, storage container 6. Simultaneously the fluidizing air escapes through the values 7, 8, and 9 connected to the closed dome covers and/or through the filter tubes 10 arranged on the bottom of the storage vehicle container. The filter cloths 11, 12, and 13 arranged below the dome cover hold back the highly dispersed material. The pressure in the travelling storage container is controlled during the filling via the manometer 14.

Abstract: A method for compacting and/or filling of pulverulent materials into rigid or flexible containers in the course of which the pulverulent material is filled into the container with the help of a pipe in relative motion to the container, and separated from the gas, for example air, transported along with the help of a separation device which surrounds the pipe and is fitted to the container cross section. The pulverulent material is retained in the container with the help of the separation device, while the gas escapes through the gas permeable separation device.

Abstract: An amplifier comprising at least one emitter-coupled transistor pair with a signal source connected in the emitter line. Amplifier non-linearities mainly caused by the second harmonic are compensated by supplying the base of at least one of the transistors with a compensation signal of suitable phase that is derived from either the input or the output signal of the amplifier. This results in a multiplication process which produces a second harmonic in the collector current of the two transistors which, with the correct phase of the compensation signal at the input, exactly compensates the second harmonic caused by the amplifier non-linearity. If the transistor pair is used for gain or volume control, the direct voltage between the bases of the two transistors, and the compensation signal, will both be varied.

Abstract: The circuit arrangement in accordance with the invention comprises an RC-element, to which the same direct voltage is applied as the amplifier. When the direct voltage is switched on or off the capacitor is either charged or discharged, the resulting oppositely directed voltages being applied to the anti-parallel base-emitter junctions of two transistors, whose collectors are interconnected. The collector voltage of these transistors serves to control a semiconductor switch included in the audio frequency branch.