Abstract: A data processing system has virtual memory addressing and includes a buffer between the working memory and the central processor. The buffer includes a data buffer divided into a plurality of banks of identical size and a plurality of tag/flag memories respectively assigned to the data banks for storing the page address. The data buffer bank and the tag/flag memories are additionally addressed, beyond the page class address, with as many further, directly connected address bits of a virtual page address as are required for the binary addressing of the individual data buffer banks. The virtual partial addressing of the buffer provides a simple addressing for the case in which memory modules of the buffer banks have a capacity beyond the page size.