Abstract: According to an embodiment, a method of operating a measurement circuit includes biasing a sense transistor to conduct current through a first conduction channel in a first direction during a first mode, injecting a measurement current into a body diode of the sense transistor during a second mode, measuring a first voltage across the sense transistor when the measurement current is injected, and determining a temperature of the sense transistor based on the first voltage. When the measurement current is injected, it is injected in a second direction opposite the first direction. The sense transistor is integrated in a semiconductor body with a load transistor having a second conduction channel, and the first conduction channel and the second conduction channel are coupled to an input node.

Abstract: The electronic device for sensing a current comprises a semiconductor chip comprising a main face, an electronic circuit integrated in the semiconductor chip, a redistribution metallization layer disposed above the main face of the semiconductor chip, a current path formed in the redistribution metallization layer, the current path forming a resistor that is connected at two resistance defining end points to the electronic circuit for sensing a current flowing through the current path, and external contact elements connected with the redistribution metallization layer for feeding a current to be sensed into the current path.

Abstract: In one example, a method includes receiving, by a first device and from a second device, power via a power line of a cable connecting the first device to the second device, wherein receiving power comprises drawing, by the first device, current from the second device. The method may also include communicating, by the first device, with the second device via the power line, wherein communicating comprises adjusting, by the first device, the amount of current drawn by the first device.

Abstract: In accordance with an embodiment, a method of operating a charging port having a power connection and a first data connection includes determining whether a compatible device is coupled to the charging port and receiving a serial data stream from the compatible device via the first data connection. The serial data stream includes a plurality of symbols representing a request for a power supply voltage and/or current, and the method further includes applying the requested power supply voltage and/or current to the power connection.

Abstract: Disclosed is an electronic circuit with a first terminal for connecting an accessory thereto, and with a functionality for detecting the presence of an accessory connected to the first terminal.

Abstract: Disclosed is an electronic circuit with a first terminal for connecting an accessory thereto, and with a functionality for detecting the presence of an accessory connected to the first terminal.

Abstract: In order to provide an interface circuit (100; 100?) as well as a method for receiving and/or for decoding, in particular for recovering, data signals (D; R, G, B), in particular high speed data signals, for example high speed sequential digital data signals, wherein at least one sampling clock signal (SC), in particular at least one multi-phase sampling clock signal (PC[n-1:0]) with n different phases, and/or the data signals (D; R, G, B) are delayed, and wherein it is possible to optimize the components, in particular the analog components, for a fixed operating frequency, it is proposed that the sampling clock signal (SC), in particular the multi-phase sampling clock signal (PC[n-1:0]), is asynchronous—to at least one interface clock signal (IC), by which the interface circuit (100; 100?), in particular the input of the interface circuit (100; 100?), can be provided with, and/or to the data signals (D; R, G, B).

Abstract: In accordance with an embodiment, a bi-directional charging circuit has a battery coupling node output configured to be coupled to a battery cell, an input coupled to a common node of the battery management system, and a controller coupled to the bi-directional charging circuit. The controller is configured to operate the bi-directional charging circuit in a charging mode to transfer charge from the common node to the battery coupling node, and operate the bi-directional charging circuit in a discharge mode to transfer change from the battery coupling node to the common node.

Abstract: A circuit arrangement is provided, the circuit arrangement including a processor; a memory circuit connected to the processor, wherein the processor is configured to access the memory circuit; a blocking circuit configured to generate one or more random wait state signals which prevent the processor from accessing the memory circuit; and an integrity checking circuit configured to check the memory circuit during a wait state period of the one or more random wait state signals.

Abstract: Disclosed is an electronic circuit with a first terminal for connecting an accessory thereto, and with a functionality for detecting the presence of an accessory connected to the first terminal.

Abstract: Illustrative methods, apparatuses and software are described for searching for an ID of a slave node within a communication network, such as a single-wire communication network. Also, illustrative embodiments of a master node and a slave node are described.

Abstract: An integrating analog to digital converter (ADC) is disclosed that comprises a Delay Locked Loop (DLL) (2, 50) which is synchronized to a reference clock signal (12). A rising edge of a clock signal therefore propagates through the DLL once each clock cycle. In use, the integrating ADC converts an analog input signal to a digital output signal dependent upon a timing measurement of an integration carried out by an integrator (4). The timing measurement is taken by reading the logical states of the individual delay cells in the DLL. This enables the position of the rising edges of the clock signal to be determined and used as a timing measurement. The timing measurement is in the form of a digital thermometer code that can be converted into a binary number.

Abstract: Illustrative methods, apparatuses and software are described for searching for an ID of a slave node within a communication network, such as a single-wire communication network. Also, illustrative embodiments of a master node and a slave node are described.

Abstract: A method operating an electronic system including sending or receiving a signal is disclosed. One embodiment includes changing a parameter of a signal from a first value to a second value after a first time duration if a logic zero is to be transmitted, and changing the parameter of the signal from the first value to the second value after a second time duration if a logic one is to be transmitted.

Abstract: A method operating an electronic system including sending or receiving a signal is disclosed. One embodiment includes changing a parameter of a signal from a first value to a second value after a first time duration if a logic zero is to be transmitted, and changing the parameter of the signal from the first value to the second value after a second time duration if a logic one is to be transmitted.

Abstract: In order to provide an interface circuit (100; 100?) as well as a method for receiving and/or for decoding, in particular for recovering, data signals (D; R, G, B), in particular high speed data signals, for example high speed sequential digital data signals, wherein at least one sampling clock signal (SC), in particular at least one multi-phase sampling clock signal (PC[n-1:0]) with n different phases, and/or the data signals (D; R, G, B) are delayed, and wherein it is possible to optimize the components, in particular the analog components, for a fixed operating frequency, it is proposed that the sampling clock signal (SC), in particular the multi-phase sampling clock signal (PC[n-1:0]), is asynchronous—to at least one interface clock signal (IC), by which the interface circuit (100; 100?), in particular the input of the interface circuit (100; 100?), can be provided with, and/or to the data signals (D; R, G, B).

Abstract: An integrating analog to digital converter (ADC) is disclosed that comprises a Delay Locked Loop (DLL) (2, 50) which is synchronized to a reference clock signal (12). A rising edge of a clock signal therefore propagates through the DLL once each clock cycle. In use, the integrating ADC converts an analog input signal to a digital output signal dependent upon a timing measurement of an integration carried out by an integrator (4). The timing measurement is taken by reading the logical states of the individual delay cells in the DLL. This enables the position of the rising edges of the clock signal to be determined and used as a timing measurement. The timing measurement is in the form of a digital thermometer code that can be converted into a binary number. By using a DLL to take a timing measurement, the effect of process and temperature variations is reduced by the closed loop feedback of the DLL. In another embodiment, a multiplying DLL (MDLL) is used.

Abstract: In the case of a method and a device for transmitting data units by way of a transmission medium that comprises at least three adjacent transmission lines, first of all a plurality of codes is supplied. Each code has a number of code sections that corresponds to the number of transmission lines of the transmission medium. Each code section has on an associated transmission line a predetermined signal value, the sum of the signal values for each transmitted code being substantially constant. For each data unit to be transmitted, a code is selected from the plurality of codes, and the selected code is supplied for transmission by way of the transmission medium. The data units and the codes to be transmitted can be supplied in accordance with a predetermined clock pulse, a new code being selected at each new clock pulse, based on the preceding code and the new data unit.

Abstract: In the case of a method and a device for transmitting data units by way of a transmission medium that comprises at least three adjacent transmission lines, first of all a plurality of codes is supplied. Each code has a number of code sections that corresponds to the number of transmission lines of the transmission medium. Each code section has on an associated transmission line a predetermined signal value, the sum of the signal values for each transmitted code being substantially constant. For each data unit to be transmitted, a code is selected from the plurality of codes, and the selected code is supplied for transmission by way of the transmission medium. The data units and the codes to be transmitted can be supplied in accordance with a predetermined clock pulse, a new code being selected at each new clock pulse, based on the preceding code and the new data unit.

Abstract: A method and device for generating a clock signal with predetermined clock signal properties firstly prepare a number of clock signals with an essentially identical frequency and with a respectively different phase relation with regard to a master clock signal in order to subsequently (on the basis of a control signal, which is prepared according to the clock signal to be generated), select predetermined clock signals from the number of prepared clock signals and to combine the selected clock signals in order to generate the desired clock signal.