Patents by Inventor Wolfgang Gartner

Wolfgang Gartner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for operating a processor bus
    Patent number: 7574543
    Abstract: A method of operating a processor bus, with which a central unit (processor) makes accesses to various peripheral units, is described. The processor bus has the ability to change the order of the accesses as a function of the operating state of the peripheral units, and the peripheral units can either reject or delay the access.
    Type: Grant
    Filed: March 28, 2002
    Date of Patent: August 11, 2009
    Assignee: Infineon Technologies AG
    Inventors: Holger Sedlak, Oliver Kniffler, Wolfgang Gärtner
  • Circuit including a built-in self-test
    Patent number: 6836866
    Abstract: A circuit includes a built-in self-test, wherein the test coverage of a tested logic circuit is improved given the utilization of a fixed standard interface. Besides a direct interface, the complex circuit has an additional indirect interface, which connects a structural test device to a functional circuit.
    Type: Grant
    Filed: October 22, 2001
    Date of Patent: December 28, 2004
    Assignee: Infineon Technologies AG
    Inventors: Jürgen Nolles, Gerd Dirscherl, Wolfgang Gärtner
  • Method for operating a processor bus
    Publication number: 20020156956
    Abstract: A method of operating a processor bus, with which a central unit (processor) makes accesses to various peripheral units, is described. The processor bus has the ability to change the order of the accesses as a function of the operating state of the peripheral units, and the peripheral units can either reject or delay the access.
    Type: Application
    Filed: March 28, 2002
    Publication date: October 24, 2002
    Inventors: Holger Sedlak, Oliver Kniffler, Wolfgang Gartner
  • Circuit including a built-in self-test
    Publication number: 20020104052
    Abstract: A circuit includes a built-in self-test, wherein the test coverage of a tested logic circuit is improved given the utilization of a fixed standard interface. Besides a direct interface, the complex circuit has an additional indirect interface, which connects a structural test device to a functional circuit.
    Type: Application
    Filed: October 22, 2001
    Publication date: August 1, 2002
    Inventors: Jurgen Nolles, Gerd Dirscherl, Wolfgang Gartner