Abstract: An inverter has two transistors driven via two capacitors. The dc operating point of the transistors are set by means of currents derived from the output currents of a reference current source. This gives identical delays for the positive and negative pulse edges of the input signal, so that, in a preferred application together with a differential amplifier used as a voltage camparator, a good high-frequency response is achieved in the range from 10 to 20 MHz.

Abstract: To adjust time delays in equidistant steps, an inverter chain is provided with an even number of static inverters of identical topology. The output of one of the even-numbered inverters is connected to the signal output via a selector switch. During suitable frequency-measuring periods, an odd number of inverters is connected to form a ring by directly coupling the output of an odd-numbered inverter to the input of the first, and a digital measuring arrangement determines the time delay of the ring-connected portion from the frequency of the ring's self-excited oscillation. The output signal of the measuring arrangement is used to adjust the time delay of the inverter chain.

Abstract: A fast MOS driver circuit for digital signals having a small current consumption and a good signal-to-noise ratio comprises an output inverter, a pre-inverter and of an enhancement-type transistor having its source-drain path connected in parallel to that of the load transistor of the output inverter (IA). The gate of the enhancement-type transistor and the gates of the load transistors of the output and pre-inverters are coupled to the output of the pre-inverter. The W/L-ratio of the enhancement-type transistor is almost the same as that of the switching transistor of the output inverter. The gates of the switching transistors are connected to one another. The load transistors are of the depletion type while the switching transistors are of the enhancement type.

Abstract: For the multiple utilization of an external IC terminal, e.g. as input for some options e.g. a testing sequence, there is provided in the IC a special clock generator for three clock signals which are combined in such a way via switches and an inverter that different potentials at the external terminal are "recognized" and converted into different binary signals.

Abstract: The ternary-binary conversion is reached by two CMOS inverters dimensioned extremely unsymmetrically with regard to their W/L ratio and connected in parallel at their inputs. By further addition of a NAND or a NOR gate the circuit can be used in an integrated circuit as option releasing stage without additional terminal for the option signal which has only to be chosen as the middle value of the ternary signal whereas its lower and upper values are the binary signals.

Abstract: An integrated clock pulse shaper showing a pair of resistivities each of which is connected in series to ground over the source drain line of one of a pair of MISFETs. The MISFETs are galvanically cross-coupled from the drain to the gate. A pair of overlapping pulse trains each of which is fed to one of the pair of resistivities, are shaped to a non-overlapping pair of pulse trains occurring at the common connection points of each transistor/resistivity pair.

Abstract: A known crystal oscillator circuit is modified to improve the starting of oscillations therein when a low supply voltage is employed. The oscillator circuit includes two complementary field effect transistors connected in a known manner to each other and a frequency determining circuit including a crystal. The modification includes a first additional field effect transistor having its drain-source path connected in parallel with the drain-source path of one of the oscillator field effect transistors or a second additional field effect transistor having its drain-source path connected in parallel with the drain-source path of the other of the oscillators field effect transistors. The first and second additional field effect transistors are of the same conductivity type as the oscillator field effect transistor it is in parallel with.

Abstract: This relates to a quartz clock having a frequency divider IC with an adjustable and programmable dividing factor. The adjustable dividing factor is reached by suppression of the pulses to be divided in such a manner that the distribution of the suppressed pulses is optimized.