Abstract: A circuit arrangement for limiting the transmission speed of binary data signals is described. A first input is supplied with associated element pulse trains which have a given pulse duration when their repetition frequency is equal to a given limit frequency. When the repetition frequency does not exceed a predetermined limit frequency, binary signals corresponding to the data signals are emitted. A first time stage, supplied with the element pulse trains, emits a first signal having a duration equal to the durations of the pulses in the element pulse trains at the predetermined limit frequency. If the aforementioned first signal occurs between two pulses of the element pulse train, a second time stage, which is supplied with the first signal, and element pulse trains, produces a second signal. The duration of the latter signal is greater than durations of the element pulse train. A blocking stage blocks the emission of binary output signals when the second signal occurs.