Abstract: A method for demodulation of a time discrete, sampled, frequency modulated digitized signal arriving as samples, each having a digital value, at a constant rate of repetition of one clock period TA per sample, including delay lines through which the signal to be demodulated are conducted, the method which includes taking three consecutive digital samples of the signal, the first sample at the initial time T and the second sample after two clock periods and a third sample taken after one clock period respectively, adding the digital value of the first and second sample forming their sum, dividing the sum by the digital value of the third sample, forming a division, the division forming a digital sample which represents a sample of the demodulated signal.

Abstract: Method for demodulating time-discrete frequency-modulated signals. The method includes combining sequential equidistant samples of a signal to be demodulated for deducing the instantaneous frequency of the signal to be demodulated. The improvement includes dividing a first vector sum of samples forming a dividend by a second vector sum of samples forming a divisor. Each sample is a complex number represented by a vector. The vector sum of the dividend has a phase that is offset from the vector sum of the divisor by a phase angle equal to n times pi, wherein n is any integer. The division of the vector sums is advantageously performed by a ROM in which all the division results have been stored and which can be accessed by the divisor and the dividend for quickly obtaining the division result. Delay lines and summing circuits are used for combining the samples into the dividend and the divisor.

Abstract: Method for digitally controlling the phase of the system clock frequency of a digital signal processing system which processes an analog signal containing a reference signal, wherein a fixed phase relation exists between the digitalized reference signal and the system clock frequency, which includes digitalizing the reference signal by sampling the analog reference signal, weighting the scanning values of the digitalized reference signal for obtaining a digital phase comparison variable, feeding the phase comparison variable through a digital PLL filter to a digitally controlled oscillator, and deriving the system clock frequency from the output signal of the digitally controlled oscillator, and an apparatus for carrying out the method.

Abstract: Method for controlling the digital chrominance signal of a color television receiver depending upon the amplitude of the burst signal and color contrast, which includes multiplying the digital chrominance signal and the burst signal in a multiplier with a given coefficient, forming a mean value of the burst amplitude from an output signal of the multiplier, comparing the mean value of the burst amplitude with a nominal value corresponding to a desired color contrast setting, and changing the given coefficient corresponding to the result of the comparison, and an apparatus for carrying out the method.

Abstract: Method for filtering the luminance signal from a CCVS television signal, which includes sampling the CCVS signal in a CTD filter with twice the color carrier frequency, converting the CCVS signal into a charge packet proportional to its voltage, dividing the charge packet into first and second charge parts in a ratio of 1:1, conducting the first and second charge parts through separate branches, delaying the first charge part relative to the second charge part by one given sampling period in the branches, and subsequently recombining the charge parts in an output channel, and an apparatus for carrying out the method.

Abstract: CTD transversal filter, for time delayed forming of a given input signal being weighted and subsequently summed for producing a filter characteristic, with weighting coefficients optionally having a negative and a positive sign, including a separate input stage for forming each desired weighting coefficient for obtaining a desired filter characteristic, the input signal being scanned by a common scanning frequency for all input stages, being converted to a charge packet proportional to its voltage and being time delayed in the input stages, the input stages for forming the negative weighting coefficients being formed in an inverting manner as compared to the input stages for forming the positive weighting coefficients, gate electrodes of the input stages, the areas of the gate electrodes of the input stages under which the charge packets are formed proportional to the input voltage, corresponding to the ratio of the absolute values of the required weighting coefficients, and a common output stage in which the