Abstract: An integrated dynamic random access memory chip is provided, the memory chip comprising a plurality of volatile memory cells for storing user data and a plurality of non-volatile rewritable memory cells for storing at least one of repair data, trimming data, sorting data and identification data.

Abstract: A method for repairing an integrated memory having first units of memory cells and second, redundant units of memory cells for replacing first units of memory cells. The first units of memory cells are tested with regard to their functionality. In the case of a defect ascertained in one of the first units, a number of redundant units is programmed as an associated cluster for replacing one or more of the first units. In this way, a repair element is formed with a cluster size corresponding to the number of redundant units. The cluster size of respective repair elements is set in a variable manner by a redundancy circuit. As a result, in a test and repair operation, a comparatively short test time of the memory is made possible in conjunction with a yield that remains good.

Abstract: A method for repairing an integrated memory having first units of memory cells and second, redundant units of memory cells for replacing first units of memory cells. The first units of memory cells are tested with regard to their functionality. In the case of a defect ascertained in one of the first units, a number of redundant units is programmed as an associated cluster for replacing one or more of the first units. In this way, a repair element is formed with a cluster size corresponding to the number of redundant units. The cluster size of respective repair elements is set in a variable manner by a redundancy circuit. As a result, in a test and repair operation, a comparatively short test time of the memory is made possible in conjunction with a yield that remains good.

Abstract: An integrated memory has addressable memory cells combined into groups of column lines and row lines. The addresses of the memory cells each include a first address part addressing the respective groups of column lines and row lines. In a method for checking operation, the memory cells are successively tested in the intersection of two groups to ensure that there are no faults. Memory cells in another group are then tested. If a match between compared first address parts of faulty memory cells exists, the address of at least one of the faulty memory cells is processed further for evaluation purposes, and the addresses of other faulty memory cells are not processed further. This permits extensive compaction of addresses of faulty memory cells.

Abstract: An integrated memory has addressable memory cells combined into groups of column lines and row lines. The addresses of the memory cells each include a first address part addressing the respective groups of column lines and row lines. In a method for checking operation, the memory cells are successively tested in the intersection of two groups to ensure that there are no faults. Memory cells in another group are then tested. If a match between compared first address parts of faulty memory cells exists, the address of at least one of the faulty memory cells is processed further for evaluation purposes, and the addresses of other faulty memory cells are not processed further. This permits extensive compaction of addresses of faulty memory cells.