Abstract: A semiconductor package includes: a lead frame having a plurality of blocks of uniform size and laterally spaced apart from one another with uniform spacing; a first semiconductor die attached to a first group of the blocks; electrical conductors connecting a plurality of input/output (I/O) terminals of the first semiconductor die to a second group of the blocks, at least some blocks of the second group being laterally spaced outward from the blocks of the first group; and a mold compound encapsulating the first semiconductor die and the electrical conductors. Corresponding methods of producing the semiconductor package are also described.

Abstract: A semiconductor package includes: a lead frame having a plurality of blocks of uniform size and laterally spaced apart from one another with uniform spacing; a first semiconductor die attached to a first group of the blocks; electrical conductors connecting a plurality of input/output (I/O) terminals of the first semiconductor die to a second group of the blocks, at least some blocks of the second group being laterally spaced outward from the blocks of the first group; and a mold compound encapsulating the first semiconductor die and the electrical conductors. Corresponding methods of producing the semiconductor package are also described.

Abstract: A semiconductor component (10) has an interposer substrate (1) as stack element of a semiconductor component stack (25). The interposer substrate (1) has, on one of the interposer substrate sides (2, 4), a semiconductor chip protected by plastics composition (12) in its side edges (22). An interposer structure (3) partly covered by a plastics composition (12) is arranged on the interposer side (2, 4) opposite to the semiconductor chip (6). Edge regions (11) of the interposer substrate (1) remain free of any plastics composition (12) and have, on both interposer sides (2, 4) external contact pads (7) which are electrically connected to one another via through contacts (8).

Abstract: A semiconductor device with a plastic package molding compound, a semiconductor chip and a leadframe is disclosed. In one embodiment, the semiconductor chip is embedded in a plastic package molding compound. The upper side of the semiconductor chip and the plastic package molding compound are arranged on a leadframe. Arranged between the leadframe and the plastic package molding compound with the semiconductor chip is an elastic adhesive layer for the mechanical decoupling of an upper region from a lower region of the semiconductor device.

Abstract: An integrated device is disclosed. In one embodiment, the integrated device includes a carrier substrate with a through hole and a contact sleeve. A circuit chip is provided with a contact pad above the carrier substrate. A conductive material electrically connects the contact pad to the contact sleeve.

Abstract: A BGA package is disclosed including a base IC structure having a base substrate, with an opening running length-wise there through. A first semiconductor chip is mounted face-down on the base substrate so the bond pads thereof are accessible through the opening. The package also includes a secondary IC structure including a secondary substrate, having an opening running there through, and a second semiconductor chip. The second chip is mounted face-down on the secondary substrate so that the bond pads thereof are accessible through the opening in the secondary substrate. An encapsulant fills the opening in the secondary substrate and forms a substantially planar surface over the underside of the secondary substrate. The substantially planar surface is mounted to the first chip of the base IC structure through an adhesive. Wires connect a conductive portion of the secondary IC structure to a conductive portion of the base IC structure.

Abstract: A semiconductor device with a plastic package molding compound, a semiconductor chip and a leadframe is disclosed. In one embodiment, the semiconductor chip is embedded in a plastic package molding compound. The upper side of the semiconductor chip and the plastic package molding compound are arranged on a leadframe. Arranged between the leadframe and the plastic package molding compound with the semiconductor chip is an elastic adhesive layer for the mechanical decoupling of an upper region from a lower region of the semiconductor device.

Abstract: An integrated circuit is disclosed. In one embodiment, the integrated circuit includes a first interface layer on a first substrate, the first interface layer including a first signal path, a second interface layer on the first interface layer, the second interface layer including a second signal path, the second signal path being coupled to the first signal path, and a second substrate on the second interface layer. In one embodiment, the second substrate includes an electronic device, the electronic device being coupled to the second signal path of the second interface layer.

Abstract: The present invention relates to a multi-chip device comprising a substrate having a first surface on which a number of first contact elements is provided, a plurality of integrated circuit chips arranged in a chip stack which is arranged on a second surface of the substrate opposing the first surface, wherein each of the chips having a surface on which a number of second contact elements are provided, wherein a first one of the chips and the second contact elements thereon is arranged such that its second contact elements are uncovered by any of the chips or by the substrate and face towards the second surface of the substrate; and connecting elements which are arranged such as to connect at least one of the first contact elements of the substrate and at least one of the second contact elements of the first chip.

Abstract: An integrated device is disclosed. In one embodiment, the integrated device includes a carrier substrate with a through hole and a contact sleeve. A circuit chip is provided with a contact pad above the carrier substrate. A conductive material electrically connects the contact pad to the contact sleeve.

Abstract: A stackable packaged chip includes a substrate with a conductive wiring formed therein or thereon. The substrate further includes a plurality of substrate contact pads arranged around a periphery portion of the substrate. A chip mounted on the substrate including contact pads that are electrically connected with the conductive wiring of the substrate, and a ring surrounding edges of the chip are also included. The ring is formed from an electrically insulating material and includes a plurality of openings, each opening adjacent a substrate contact pad to allow for electrical connection to the chip though the substrate contact pad.

Abstract: A BGA package is disclosed including a base IC structure having a base substrate, with an opening running length-wise there through. A first semiconductor chip is mounted face-down on the base substrate so the bond pads thereof are accessible through the opening. The package also includes a secondary IC structure including a secondary substrate, having an opening running there through, and a second semiconductor chip. The second chip is mounted face-down on the secondary substrate so that the bond pads thereof are accessible through the opening in the secondary substrate. An encapsulant fills the opening in the secondary substrate and forms a substantially planar surface over the underside of the secondary substrate. The substantially planar surface is mounted to the first chip of the base IC structure through an adhesive. Wires connect a conductive portion of the secondary IC structure to a conductive portion of the base IC structure.

Abstract: The present invention relates to an integrated chip device in a package, including an integrated chip, a substrate comprising a redistribution wiring, a contact element and a contact pad on a common surface of the substrate, wherein the contact element is in electrical contact with the contact pad, wherein the substrate is divided in at least two parts each of which is securely attached to a respective portion of the chip to form the device, wherein between at least two of the parts of the substrate a gap is provided to accommodate a thermal expansion of at least one of the parts of the substrate, a bond wire which is provided to connect the contact pad and the further contact pad of the substrate with the integrated chip through the gap.

Abstract: A method of stacking semiconductor chips includes providing four semiconductor chips that each include a top surface with central bond pads. Each of the bond pads is electrically coupled to second bond pads located in a peripheral portion of the semiconductor chip through a conductive layer. The first and the second semiconductor chips are arranged alongside one another on a carrier substrate. The second bond pads from the first and second semiconductor chips are bonded to corresponding landing pads on the substrate. The third semiconductor chip is then stacked over the first semiconductor chip and the fourth semiconductor chip over the second semiconductor chip. The second bond pads of the third and fourth semiconductor chips can then be bonded to contact pads of the substrate. The substrate can then be separated into a first stack that includes the first and third semiconductor chips and a second stack that includes the second and fourth semiconductor chips.

Abstract: A semiconductor component (10) has an interposer substrate (1) as stack element of a semiconductor component stack (25). The interposer substrate (1) has, on one of the interposer substrate sides (2, 4), a semiconductor chip protected by plastics composition (12) in its side edges (22). An interposer structure (3) partly covered by a plastics composition (12) is arranged on the interposer side (2, 4) opposite to the semiconductor chip (6). Edge regions (11) of the interposer substrate (1) remain free of any plastics composition (12) and have, on both interposer sides (2, 4) external contact pads (7) which are electrically connected to one another via through contacts (8).

Abstract: A stackable packaged chip includes a substrate with a conductive wiring formed therein or thereon. The substrate further includes a plurality of substrate contact pads arranged around a periphery portion of the substrate. A chip mounted on the substrate including contact pads that are electrically connected with the conductive wiring of the substrate, and a ring surrounding edges of the chip are also included. The ring is formed from an electrically insulating material and includes a plurality of openings, each opening adjacent a substrate contact pad to allow for electrical connection to the chip though the substrate contact pad.

Abstract: The present invention relates to a multi-chip device comprising a substrate having a first surface on which a number of first contact elements is provided, a plurality of integrated circuit chips arranged in a chip stack which is arranged on a second surface of the substrate opposing the first surface, wherein each of the chips having a surface on which a number of second contact elements are provided, wherein a first one of the chips and the second contact elements thereon is arranged such that its second contact elements are uncovered by any of the chips or by the substrate and face towards the second surface of the substrate; and connecting elements which are arranged such as to connect at least one of the first contact elements of the substrate and at least one of the second contact elements of the first chip.

Abstract: An electronic component has a chip stack with a first semiconductor chip, a second semiconductor chip, and a large number of flat conductors configured in between the first semiconductor chip and the a second semiconductor chip. The flat conductors have a central section on which the semiconductor chips are mounted. First bonding connections connect the first semiconductor chip to inner sections of the flat conductors. Second bonding connections connect the second semiconductor chip to transitional sections of the flat conductors. The outer sections of the flat conductors project out of a package.

Abstract: A stack arrangement of discrete components includes a carrier substrate and at least two discrete components, e.g., memory chips. The carrier substrate has line conductor structures and contact pads. Each of the discrete components includes centrally disposed bond pads and a metallic coating, which is electrically connected to the centrally disposed bond pads. The metallic coating is disposed on an active surface area of each discrete component. A protective structure overlies a central region of the discrete component. In the preferred embodiment, the metallic coatings of each discrete component are identical. Preferably, the discrete components are stacked on the carrier substrate so as to have the same orientation, so that the protective structure serves as a spacer between the discrete components. Further, the metallic coating is electrically coupled to the carrier substrate.

Abstract: The invention relates to an electronic device having a stack of semiconductor chips, and to a method for the production thereof. A first semiconductor chip is arranged on a rewiring substrate, and at least one semiconductor stack chip is arranged on the first semiconductor chip. A rewiring plane is arranged between the semiconductor chips. The contact areas of the semiconductor chips are connected to external contacts of the device by the rewiring plane and the rewiring substrate.