Abstract: An apparatus for and method of generating a signal having a programmable period and a programmable duty cycle. The apparatus includes an update sequencer circuit. The update sequencer circuit is configured to detect an updated period value and an updated duty cycle value, and to receive a period match signal, and in accordance therewith selectively generate a period write signal and a duty cycle write signal. A storage element is configured to receive the updated period value, the updated duty cycle value, the period write signal, and the duty cycle write signal, and in accordance therewith replace a period value with the updated period value and a duty cycle value with the updated duty cycle value. The update sequencer circuit eliminates the requirement for associated software to have a polling loop or an interrupt.

Abstract: A level detection circuit, such as a Schmitt trigger circuit, has an input threshold voltage which varies depending upon the detection circuit output. The circuit includes a level detection stage, circuitry for switching the level detection stage between an active and a standby mode and a storage device for storing data indicative of the input threshold voltage when the level detection stage is in the standby mode and for controlling the level detection stage using the stored data so that the stage will retain the same input threshold voltage that existed when the level detection stage was switched to the standby mode.

Abstract: An input cell circuit for an integrated circuit for use in a mixed signal mode where an input pin may receive either digital or analog signals. The circuit solves the problem where several such pins are used in a mixed signal mode and share a common internal bus. Such input signals will cause erratic values on the common analog bus, if any given input pin is used as a digital input signal and the voltage on that input pin exceeds the supply voltage by the base-emitter voltage of the parasitic transistor in the P-channel transistor in a pass gate in the associated input cell. This problem is solved by adding a second P-channel transistor to the pass gate and also adding an N-channel transistor connected to a node between the two P-channel transistors, as well as adding an input resistor.

Abstract: An input cell circuit for an integrated circuit for use in a mixed signal mode where an input pin may receive either digital or analog signals. The circuit solves the problem where several such pins are used in a mixed signal mode and share a common internal bus. Such input signals will cause erratic values on the common analog bus, if any given input pin is used as a digital input signal and the voltage on that input pin exceeds the supply voltage by the base-emitter voltage of the parasitic transistor in the P-channel transistor in a pass gate in the associated input cell. This problem is solved by adding a second P-channel transistor to the pass gate and also adding an N-channel transistor connected to a node between the two P-channel transistors, as well as adding an input resistor.