Abstract: A processor device includes a clock generation unit, a processor unit, a main memory, a processor bus, and also a bus control device having an interface for a crossover bus to at least one further processor device. The bus control device monitors processor device data access through the processor bus, interchanges signals concerning data access through the crossover bus, evaluates them and outputs an error signal based on the evaluation result. In a processor system including at least two processor devices connected to one another through the crossover bus, the processor units are started in synchronism. The bus control devices in the processor devices interchange signals through the crossover bus upon each data access operation by the processor units, and output an error signal if there is no correspondence. If there is an error in one processor device, operation of the processor system is continued on the other processor device or devices.

Abstract: A processor device includes a clock generation unit, a processor unit, a main memory, a processor bus, and also a bus control device having an interface for a crossover bus to at least one further processor device. The bus control device monitors processor device data access through the processor bus, interchanges signals concerning data access through the crossover bus, evaluates them and outputs an error signal based on the evaluation result. In a processor system including at least two processor devices connected to one another through the crossover bus, the processor units are started in synchronism. The bus control devices in the processor devices interchange signals through the crossover bus upon each data access operation by the processor units, and output an error signal if there is no correspondence. If there is an error in one processor device, operation of the processor system is continued on the other processor device or devices.