Abstract: TSV devices with p-n junctions that are planar have superior performance in breakdown and current handling. Junction diode assembly formed in enclosed trenches occupies less chip area compared with junction-isolation diode assembly in the known art. Diode assembly fabricated with trenches formed after the junction formation reduces fabrication cost and masking steps increase process flexibility and enable asymmetrical TSV and uni-directional TSV functions.

Abstract: TSV devices with p-n junctions that are planar have superior performance in breakdown and current handling. Junction diode assembly formed in enclosed trenches occupies less chip area compared with junction-isolation diode assembly in the known art. Diode assembly fabricated with trenches formed after the junction formation reduces fabrication cost and masking steps increase process flexibility and enable asymmetrical TSV and uni-directional TSV functions.

Abstract: The integrated protection circuit according to the invention for ESD protecting an circuit device having at least one pad, e.g. a I/O pad, comprises a first transistor (MPI) whose control outputs are connected between the pad (2, 3) and the control input of a clamp transistor (MN4). The control outputs of the clamp transistor (MN4) are connected between the pad (2, 3) and a reference terminal (4). The protection circuit further comprises a second transistor (MN3) whose control outputs are connected between the control output of the first transistor (.MP 1) and the reference terminal (4). Finally the protection circuit also comprises time-delay elements (R, MN 1) connected between a supply voltage terminal (1) and the control inputs of the first transistor (MP I) and the second transistor (MN3).

Abstract: In one aspect, a method for protection of an integrated circuit device includes but is not limited to detecting a first current in the integrated circuit device, wherein the first current is caused by a second current; and shunting the second current away from the integrated circuit device in response to detecting the first current. Such detecting may include but not be limited to detecting the first current by detecting a voltage drop across a sensing resistor, which may include but not be limited to using at least two sensing transistors. Such shunting may include but not be limited to using at least one shunting transistor.

Abstract: In one aspect, a method for protection of an integrated circuit device includes but is not limited to detecting a first current in the integrated circuit device, wherein the first current is caused by a second current; and shunting the second current away from the integrated circuit device in response to detecting the first current. Such detecting may include but not be limited to detecting the first current by detecting a voltage drop across a sensing resistor, which may include but not be limited to using at least two sensing transistors. Such shunting may include but not be limited to using at least one shunting transistor.

Abstract: Apparatus (10) comprising a level shifter (15) connectable to a signal input (1) for receiving an input signal (s(t)) with a negative signal swing. The level shifter (15) provides for a DC shift of the input signal (s(t)) to provide an output signal (r(t)) with positive signal swing. The level shifter (15) comprises an amplifier (17) with a first input (11), a second input (12), and an output (13). A first capacitor (C1), a second capacitor (C2), a reference voltage supply (16), and a transistor (14; 74) serving as a switch, are arranged in a network as follows: the first capacitor (C1) is arranged between the signal input (1) and the first input (11), the second capacitor (C2) is arranged in a feedback-loop (18) between the output (13) and the first input (11), and the reference voltage supply (16) is connected to the second input (12). The transistor (14) is arranged in a branch (19) that bridges the second capacitor (C2), whereby a control signal (CNTRL) is applicable to a gate (14.

Abstract: The integrated protection circuit according to the invention for ESD protecting an circuit device having at least one pad, e.g. a I/O pad, comprises a first transistor (MPI) whose control outputs are connected between the pad (2, 3) and the control input of a clamp transistor (MN4). The control outputs of the clamp transistor (MN4) are connected between the pad (2, 3) and a reference terminal (4). The protection circuit further comprises a second transistor (MN3) whose control outputs are connected between the control output of the first transistor (.MP 1) and the reference terminal (4). Finally the protection circuit also comprises time-delay elements (R, MN 1) connected between a supply voltage terminal (1) and the control inputs of the first transistor (MP I) and the second transistor (MN3).

Abstract: Apparatus (10) comprising a level shifter (15) connectable to a signal input (1) for receiving an input signal (s(t)) with a negative signal swing. The level shifter (15) provides for a DC shift of the input signal (s(t)) to provide an output signal (r(t)) with positive signal swing. The level shifter (15) comprises an amplifier (17) with a first input (11), a second input (12), and an output (13). A first capacitor (C1), a second capacitor (C2), a reference voltage supply (16), and a transistor (14; 74) serving as a switch, are arranged in a network as follows: the first capacitor (C1) is arranged between the signal input (1) and the first input (11), the second capacitor (C2) is arranged in a feedback-loop (18) between the output (13) and the first input (11), and the reference voltage supply (16) is connected to the second input (12). The transistor (14) is arranged in a branch (19) that bridges the second capacitor (C2), whereby a control signal (CNTRL) is applicable to a gate (14.

Abstract: The invention is a method and a computer program product for checking an integrated circuit for electrostatic discharge (ESD) robustness at the design level and comprises essentially the check of the layout of the integrated circuit against a set of rules defining one or more transistor geometric and/or electrical and/or material values and generating an output or report of this check. This method can check automatically a complete IC design layout at any design level. An exemplary design is an ESD protection layout, a design block or a complete IC design.

Abstract: An adjusting apparatus for one or more headlight reflectors (1) has first and second miter gear mechanisms (4, 12), each of which includes a toothed-gear pair. The reflector can be pivoted about an axis by a rotation device, or knob, on the exterior of the housing. The two miter gear mechanisms are coupled by means of a rigid shaft (13) which is positioned in a bearing box (9) formed in a housing rearward wall (7). The shaft carries at each of its free ends a shaft toothed-gear of the respective first and second miter gear mechanisms and is held radially in the bearing box by means of girding elements of the toothed-gears (5, 15) whose teeth engage with the teeth of the shaft toothed-gears.