Abstract: The method controls the sequence (Q) of accesses (Z) of a processor (MP) to an allocated memory (SP) that is formed by at least two individually addressable, static sub-memories or, respectively, memory banks (SRAM 0, 1). Using a drive logic (ASL) inserted between the processor (MP) and, for example, two sub-memories (SRAM 0, 1), a first memory address (sa1) is switched in conformity with an access cycle to the addressed sub-memory (SRAM 0, 1) in a first access (Z) of a sequence (Q), a memory link address (sfa1) for the further sub-memories (SRAM 0, 1) is formed, is switched thereto and a reading or writing of a data (d) is initiated based on the criterion of the status information (sti). Subsequently, the sub-memories (SRAM 0, 1) are cyclically successively driven, a respective data (d) is read or stored using an intermediate memory (ZSP) and a memory link address (sfa2, 3) is respectively formed such that the two sub-memories (SRAM 0, 1) are successively and cyclically driven.

Abstract: In a multi-processor system in which a plurality of microprocessor systems are allocated to a common multi-processor bus in cyclical fashion in a sequence prescribed by priority characterizing numbers assigned to said systems, the priority allocation of bus access is overlaid by a further method that coordiantes the access fo a microprocessor system to a region storing a common data base in a common memory. One of the microprocessor systems functions as the main processor system and is authorized to up-date the data base and all other microprocessor systems function as subsidiary procesors which can read the data base information. Before its access, every microprocessor system accessing the data base communicates a status signal to the other micro-processor systems, this preventing the main processor system from up-dating the data base while one of the subsidiary processor systems is already reading the data base information.

Abstract: Proceeding from a known method and apparatus for expanding the address for accessing a main memory by a central controller of a switching system, a determination is made in a comparator as to whether the address information of the high-order address lines or address registers of the expansion device with respect to a preceding main memory access changes in comparison to the current main memory access. When coincidence is present, the high-order portion of the main memory address in the preceding main memory access stored in an address register is immediately used for the formation of the overall main memory address.