Abstract: The digital phase detector detects a phase shift between a comparison clock pulse signal (VT) and a reference clock pulse signal (RT). It includes logic gates (STO,STA) for generating start and stop pulses from respective successive pulses of the comparison and reference clock pulse signals (RT,VT). A counter (ZG,Z) counts the pulses of a counter clock pulse signal (ZT) of a higher frequency in a time window between the start signal and the subsequent stop signal. The counter value of the counter is a measure of the phase shift between the comparison and reference clock pulse signals (VT,RT). Quantization errors in the phase shift signal are considerably reduced by providing a logical gate (VZ) for determining the sign of the phase shift and a device (.mu.P) for adding a constant, advantageously 0.5, to the counter value.