Abstract: A method for designing a first vertical MOS power transistor having a specified design power level. The method comprises the steps of composing a layout of the vertical MOS power transistor as a combination of at least partly differing layout part pieces, each of the part pieces having known design data, the part pieces including at least one first layout part piece comprising a given number of single transistor cells, and adjusting the specified design power level of the first vertical MOS power transistor by using the known design data of the part pieces and based on the layout combination of the part pieces.

Abstract: The invention relates to a simulation and/or layout process for vertical power transistors as DMOS or IGBT with variable channel width and variable gate drain capacity which can be drawn and/or designed by the designer with the respectively desired parameters of channel width and gate drain capacity and the parameters of volume resistance and circuit speed, which are correlated therewith, and whose electrical parameters can be described as a function of the geometrical gate electrode design. Here, both discrete and integrated vertical transistors may be concerned.

Abstract: A method for designing a first vertical MOS power transistor having a specified design power level. The method comprises the steps of composing a layout of the vertical MOS power transistor as a combination of at least partly differing layout part pieces, each of the part pieces having known design data, the part pieces including at least one first layout part piece comprising a given number of single transistor cells, and adjusting the specified design power level of the first vertical MOS power transistor by using the known design data of the part pieces and based on the layout combination of the part pieces.

Abstract: A method for designing a first vertical MOS power transistor having a specified design power level. The method comprises the steps of composing a layout of the vertical MOS power transistor as a combination of at least partly differing layout part pieces, each of the part pieces having known design data, the part pieces including at least one first layout part piece comprising a given number of single transistor cells, and adjusting the specified design power level of the first vertical MOS power transistor by using the known design data of the part pieces and based on the layout combination of the part pieces.

Abstract: The invention relates to a simulation and/or layout process for vertical power transistors as DMOS or IGBT with variable channel width and variable gate drain capacity which can be drawn and/or designed by the designer with the respectively desired parameters of channel width and gate drain capacity and the parameters of volume resistance and circuit speed, which are correlated therewith, and whose electrical parameters can be described as a function of the geometrical gate electrode design. Here, both discrete and integrated vertical transistors may be concerned.

Abstract: A method for designing a first vertical MOS power transistor having a specified design power level. The method comprises the steps of composing a layout of the vertical MOS power transistor as a combination of at least partly differing layout part pieces, each of the part pieces having known design data, the part pieces including at least one first layout part piece comprising a given number of single transistor cells, and adjusting the specified design power level of the first vertical MOS power transistor by using the known design data of the part pieces and based on the layout combination of the part pieces.

Abstract: A circuit arrangement for bridging high voltages using a switching signal as a dynamic voltage level shifter includes switching signal sequences that can be processed or provided at different voltage levels. Thus, any technology for integrated high-voltage circuit involving any isolation method can be used to produce the circuit arrangements. The circuit arrangements make available signal levels with conventional voltage levels of between 3 V and 15 V at another voltage level, using a potential differential of a few volts up to several hundred volts, depending on the technology and application used. The potential differential between the input voltage level, or voltage transmitter and the output voltage level, or voltage receiver, can be either positive or negative, or can vary in intensity.