Patents by Inventor Wolfgang Molzer
Wolfgang Molzer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230317544Abstract: Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. For example, in some embodiments, a microelectronic assembly may include a substrate having a first surface including a cavity and an opposing second surface; a die above the cavity and electrically coupled to the second surface of the substrate; a circuit board attached to the substrate; and a cooling apparatus at least partially nested in the cavity, wherein the cooling apparatus is in thermal contact with the die. In some embodiments, a microelectronic assembly may include a circuit board having a surface including a cavity; a substrate having a first surface attached to the circuit board and a die electrically coupled to an opposing second surface; and a cooling apparatus at least partially nested in the cavity, wherein the cooling apparatus is in thermal contact with the die.Type: ApplicationFiled: March 21, 2022Publication date: October 5, 2023Applicant: Intel CorporationInventors: Jan Proschwitz, Sonja Koller, Thomas Wagner, Vishnu Prasad, Wolfgang Molzer
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Publication number: 20230307313Abstract: A semiconductor package comprises a package substrate comprised of at least a first layer of dielectric material including a portion of diamond dust material. The diamond dust material is comprised of diamond dust particles. The semiconductor package includes at least one electrical connection coupled through layers of the package substrate.Type: ApplicationFiled: March 24, 2022Publication date: September 28, 2023Inventors: Carlton Hanna, Wolfgang Molzer, Stefan Reif, Georg Seidemann, Stephan Stoeckl, Pouya Talebbeydokhti
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Publication number: 20230298953Abstract: Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. In some embodiments, a microelectronic assembly may include a substrate; a lid surrounding an individual die, wherein the lid includes a planar portion and two or more sides extending from the planar portion, and wherein the individual die is electrically coupled to the substrate by interconnects; and a material surrounding the interconnects and coupling the two or more sides of the lid to the substrate.Type: ApplicationFiled: March 20, 2022Publication date: September 21, 2023Applicant: Intel CorporationInventors: Pouya Talebbeydokhti, Mohan Prashanth Javare Gowda, Sonja Koller, Stephan Stoeckl, Thomas Wagner, Wolfgang Molzer
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Publication number: 20230300975Abstract: Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. For example, in some embodiments, a microelectronic assembly may include a substrate having a surface including a first cavity; a first die at least partially nested in the first cavity and electrically coupled to the substrate; and a circuit board having a surface including a second cavity, wherein the surface of the substrate is electrically coupled to the surface of the circuit board, and wherein the first die extends at least partially into the second cavity in the circuit board.Type: ApplicationFiled: March 21, 2022Publication date: September 21, 2023Applicant: Intel CorporationInventors: Jan Proschwitz, Sonja Koller, Thomas Wagner, Vishnu Prasad, Wolfgang Molzer
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Publication number: 20230268291Abstract: Embodiments of a microelectronic assembly include a package substrate comprising: a first layer comprising a first plurality of mutually parallel channels of a first material; a second layer comprising columns of the first material; and a third layer comprising a second plurality of mutually parallel channels of the first material, the second plurality of mutually parallel channels being orthogonal to the first plurality of mutually parallel channels. The second layer is between the first layer and the third layer, at least some columns extend between and contact the first plurality of mutually parallel channels and the second plurality of mutually parallel channels, and at least a portion of the first layer, the second layer and the third layer comprises a second material different from the first material.Type: ApplicationFiled: February 24, 2022Publication date: August 24, 2023Applicant: Intel CorporationInventors: Mohan Prashanth Javare Gowda, Stephan Stoeckl, Sonja Koller, Wolfgang Molzer, Thomas Wagner, Pouya Talebbeydokhti
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Publication number: 20230268286Abstract: Embodiments of a microelectronic assembly comprise a package substrate, including: a first layer comprising a first plurality of mutually parallel channels of a first material; a second layer comprising columns of the first material; and a third layer comprising a second plurality of mutually parallel channels of the first material. The second layer is between the first layer and the third layer, at least some columns extend between and contact the first plurality of mutually parallel channels and the second plurality of mutually parallel channels, and at least a portion of the first layer, the second layer, and the third layer comprises a second material different from the first material.Type: ApplicationFiled: February 24, 2022Publication date: August 24, 2023Applicant: Intel CorporationInventors: Mohan Prashanth Javare Gowda, Stephan Stoeckl, Thomas Wagner, Sonja Koller, Wolfgang Molzer, Pouya Talebbeydokhti
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Publication number: 20230197566Abstract: A semiconductor die is provided. The semiconductor die includes a plurality of transistors arranged at a front side of a semiconductor substrate and an electrically conductive structure and a trench extending from a backside of the semiconductor substrate into the semiconductor substrate. A length of the trench is equal or larger than a lateral dimension of the semiconductor substrate.Type: ApplicationFiled: December 17, 2021Publication date: June 22, 2023Inventors: Bernd WAIDHAS, Wolfgang MOLZER, Peter BAUMGARTNER, Thomas WAGNER, Joachim SINGER, Klaus HEROLD, Michael LANGENBUCH
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Publication number: 20230197615Abstract: IC devices including transformers that includes two electrically conductive layers are disclosed. An example IC device includes a transformer that includes a first coil, a second coil, and a magnetic core coupled to the two coils. The first coil includes a portion or the whole electrically conductive layers at the backside of a support structure. The second coil includes a portion or the whole electrically conductive layers at either the frontside or the backside of the support structure. The two coils may have a lateral coupling, vertical coupling, or other types of couplings. The transformer is coupled to a semiconductor device over or at least partially in the support structure. The semiconductor device may be at the frontside of the support structure. The transformer can be coupled to the semiconductor device by TSVs. The IC device may also include BPRs that facilitate backside power delivery to the semiconductor device.Type: ApplicationFiled: December 21, 2021Publication date: June 22, 2023Applicant: Intel CorporationInventors: Peter Baumgartner, Bernd Waidhas, Wolfgang Molzer, Klaus Herold, Joachim Singer, Michael Langenbuch, Thomas Wagner
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Publication number: 20230197599Abstract: IC devices including BPRs with integrated decoupling capacitance are disclosed. An example IC device includes a first layer comprising a transistor and a support structure adjoining the first layer. The support structure includes BPRs, which are power rails buried in the support structure, and a decoupling capacitor based on the BPRs. The conductive cores of the BPRs are the electrodes of the decoupling capacitor. The dielectric barriers of the BPRs can be the dielectric of the decupling capacitor. The dielectric of the decupling capacitor may also include a dielectric element between the BPRs. Additionally or alternatively, the IC device includes another decoupling capacitor at the backside of the support structure. The other decoupling capacitor is coupled to the BPRs and can provide additional decoupling capacitance for stabilizing power supply facilitated by the BPRs.Type: ApplicationFiled: December 17, 2021Publication date: June 22, 2023Applicant: Intel CorporationInventors: Bernd Waidhas, Harald Gossner, Wolfgang Molzer, Georg Seidemann, Michael Langenbuch, Martin Ostermayr, Joachim Singer, Thomas Wagner, Klaus Herold
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Publication number: 20230197644Abstract: A semiconductor package comprises a semiconductor die and a wiring structure, which is electrically connected to the semiconductor die. Further, the semiconductor package comprises a magnetic material. The magnetic material embeds and/or encircles a portion of the wiring structure.Type: ApplicationFiled: December 17, 2021Publication date: June 22, 2023Inventors: Wolfgang MOLZER, Harald GOSSNER, Georg SEIDEMANN, Bernd WAIDHAS, Michael LANGENBUCH
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Publication number: 20230094594Abstract: A semiconductor device is disclosed, comprising a first semiconductor die comprising a plurality of transistors; a second semiconductor die comprising power supply circuitry configured to generate a supply voltage for the plurality of transistors of the first semiconductor die; and a heat spreader structure. A power supply routing for a reference voltage or a power supply voltage which extends from the heat spreader structure through the second semiconductor die to the first semiconductor die.Type: ApplicationFiled: September 24, 2021Publication date: March 30, 2023Inventors: Wolfgang MOLZER, Klaus HEROLD, Joachim SINGER, Peter BAUMGARTNER, Michael LANGENBUCH, Thomas WAGNER, Bernd WAIDHAS
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Publication number: 20210193594Abstract: Embodiments disclosed herein include semiconductor packages. In a particular embodiment, the semiconductor package is a wafer level chip scale package (WLCSP). In an embodiment, the WLCSP comprises a die. In an embodiment, the die comprises an active surface and a backside surface. The die has a first coefficient of thermal expansion (CTE). In an embodiment, the WLCSP further comprises a channel into the die. In an embodiment, the channel is filled with a stress relief material, where the stress relief material has a second CTE that is greater than the first CTE.Type: ApplicationFiled: December 19, 2019Publication date: June 24, 2021Inventors: Stephan STOECKL, Wolfgang MOLZER, Georg SEIDEMANN, Bernd WAIDHAS
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Patent number: 10845073Abstract: A method (300) for temperature control in a radio receiver includes: receiving (301) a sequence of radio subframes, wherein each radio subframe (200) in the sequence of radio subframes comprises at least one control region (201) and at least one data region (202); monitoring (302) temperature information indicating a system temperature (T) of the radio receiver; and if the temperature information indicates that the system temperature (T) exceeds (303) a first threshold (T1), transition (304) to a second state (305) in which receiving the at least one data region is disabled.Type: GrantFiled: November 10, 2016Date of Patent: November 24, 2020Assignee: Apple Inc.Inventors: Sven Dortmund, Kenan Kocagoez, Jose A. Cesares Cano, Wolfgang Molzer, Matthias Obermeier
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Publication number: 20170167745Abstract: A method (300) for temperature control in a radio receiver includes: receiving (301) a sequence of radio subframes, wherein each radio subframe (200) in the sequence of radio subframes comprises at least one control region (201) and at least one data region (202); monitoring (302) temperature information indicating a system temperature (T) of the radio receiver; and if the temperature information indicates that the system temperature (T) exceeds (303) a first threshold (T1), transition (304) to a second state (305) in which receiving the at least one data region is disabled.Type: ApplicationFiled: November 10, 2016Publication date: June 15, 2017Inventors: SVEN DORTMUND, KENAN KOCAGOEZ, JOSE A. CESARES CANO, WOLFGANG MOLZER, MATTHIAS OBERMEIER
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Patent number: 9583595Abstract: Disclosed herein are Lateral Diffused Metal Oxide Semiconductor (LDMOS) device and trench isolation related devices, methods, and techniques. In one illustration, a doped region is formed within a semiconductor substrate. A trench isolation region is formed within the doped region. The doped region and the trench isolation region are part of a Lateral Diffused Metal Oxide Semiconductor (LDMOS) device. The trench isolation region or an interface between the trench isolation region and the doped region is configured to reduce low frequency noise in the LDMOS device.Type: GrantFiled: September 2, 2015Date of Patent: February 28, 2017Assignee: Infineon Technologies AGInventors: Giovanni Calabrese, Domagoj Siprak, Wolfgang Molzer, Uwe Hodel
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Patent number: 9564400Abstract: Embodiments of the present description include stacked microelectronic dice embedded in a microelectronic substrate and methods of fabricating the same. In one embodiment, at least one first microelectronic die is attached to a second microelectronic die, wherein an underfill material is provided between the second microelectronic die and the at least one first microelectronic die. The microelectronic substrate is then formed by laminating the first microelectronic die and the second microelectronic die in a substrate material.Type: GrantFiled: January 28, 2016Date of Patent: February 7, 2017Assignee: Intel CorporationInventors: Reinhard Mahnkopf, Wolfgang Molzer, Bernd Memmler, Edmund Goetz, Hans-Joachim Barth, Sven Albers, Thorsten Meyer
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Publication number: 20160225694Abstract: A through silicon via is described that has conductivity at high frequencies. In one example, the via includes a channel through at least a portion of a silicon die. A first conductive layer has a first electrical conductivity. A second conductive layer covers the outer surface of the first conductive layer and has a second electrical conductivity higher than the first electrical conductivity.Type: ApplicationFiled: June 27, 2013Publication date: August 4, 2016Inventors: Hans-Joachim BARTH, Reinhard MAHNKOPF, Wolfgang MOLZER, Harald GOSSNER, Christian MUELLER
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Patent number: 9373588Abstract: Embodiments of the present description include stacked microelectronic dice embedded in a microelectronic substrate and methods of fabricating the same. In one embodiment, at least one first microelectronic die is attached to a second microelectronic die, wherein an underfill material is provided between the second microelectronic die and the at least one first microelectronic die. The microelectronic substrate is then formed by laminating the first microelectronic die and the second microelectronic die in a substrate material.Type: GrantFiled: September 24, 2013Date of Patent: June 21, 2016Assignee: Intel CorporationInventors: Reinhard Mahnkopf, Wolfgang Molzer, Bernd Memmler, Edmund Goetz, Hans-Joachim Barth, Sven Albers, Thorsten Meyer
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Publication number: 20160148920Abstract: Embodiments of the present description include stacked microelectronic dice embedded in a microelectronic substrate and methods of fabricating the same. In one embodiment, at least one first microelectronic die is attached to a second microelectronic die, wherein an underfill material is provided between the second microelectronic die and the at least one first microelectronic die. The microelectronic substrate is then formed by laminating the first microelectronic die and the second microelectronic die in a substrate material.Type: ApplicationFiled: January 28, 2016Publication date: May 26, 2016Applicant: Intel CorporationInventors: Reinhard Mahnkopf, Wolfgang Molzer, Bernd Memmler, Edmund Goetz, Hans-Joachim Barth, Sven Albers, Thorsten Meyer
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Patent number: 9252077Abstract: Via are described for radio frequency antenna connections related to a package. In one example, a package has a package substrate, a die attached to the package substrate, and a conductive via from the package substrate to an external surface of the package to make a radio frequency connection between the antenna and the package substrate.Type: GrantFiled: September 25, 2013Date of Patent: February 2, 2016Assignee: Intel CorporationInventors: Wolfgang Molzer, Edmund Goetz, Reinhard Mahnkopf, Bernd Memmler