Abstract: An apparatus for generating an output signal having a higher frequency than a first signal received from a first external connector of a test equipment associated to a first channel and a second signal received on a second external connector of the test equipment associated to a second channel, having a first connector adapted to be connected to said first external connector, and adapted to receive the first signal, a second connector adapted to be connected to said second external connector, and adapted to receive the second signal, wherein the first and second signals are out of phase, an output to be connected to the device under test, and a passive circuit for combining the signals received at said first and second connector into the output signal and for providing said output signal to said output.

Abstract: A memory apparatus includes a memory module array having several memory modules. Each memory module has a synchronization connection for receiving a synchronization signal for synchronizing the memory module relative to the other memory modules in the memory module array. This enables combining data bursts read from the memory modules into a data stream.

Abstract: A circuit configuration has a calibration circuit, which is connected to terminals for two digital signals and has outputs for two digital output signals which are each derived from one of the digital signals. The calibration circuit effects temporal control of a switching edge of one of the output signals using a control value. A comparison circuit generates a comparison signal which indicates that one of the output signals has a switching edge first relative to the other output signal. The calibration circuit has a control input, through which the control value, which is stored in a storage circuit, can be set using the state of the comparison signal of the comparison circuit. The circuit configuration makes it possible to compensate undesirable propagation time differences between the digital signals.

Abstract: A method and a circuit configuration for a dynamic semiconductor memory are described in which, in order to reduce the parasitic coupling effects between two adjacent bit lines, in particular between a read line and a reference line, the adjacent line is put at a predetermined potential during the read operation. As a result, the read signal, which is very small in the worst-case scenario, is not adversely influenced by the coupling capacitance, since the inactive adjacent line acts as capacitive shielding. Advantageously, the read signals of the various active bit lines cannot mutually influence one another. A further refinement of the invention provides for the potential to be kept at the magnitude of the precharge state.

Abstract: A memory apparatus includes a memory module array having several memory modules. Each memory module has a synchronization connection for receiving a synchronization signal for synchronizing the memory module relative to the other memory modules in the memory module array. This enables combining data bursts read from the memory modules into a data stream.

Abstract: A method and a circuit configuration for a dynamic semiconductor memory are described in which, in order to reduce the parasitic coupling effects between two adjacent bit lines, in particular between a read line and a reference line, the adjacent line is put at a predetermined potential during the read operation. As a result, the read signal, which is very small in the worst-case scenario, is not adversely influenced by the coupling capacitance, since the inactive adjacent line acts as capacitive shielding. Advantageously, the read signals of the various active bit lines cannot mutually influence one another. A further refinement of the invention provides for the potential to be kept at the magnitude of the precharge state.

Abstract: A circuit configuration has a calibration circuit, which is connected to terminals for two digital signals and has outputs for two digital output signals which are each derived from one of the digital signals. The calibration circuit effects temporal control of a switching edge of one of the output signals using a control value. A comparison circuit generates a comparison signal which indicates that one of the output signals has a switching edge first relative to the other output signal. The calibration circuit has a control input, through which the control value, which is stored in a storage circuit, can be set using the state of the comparison signal of the comparison circuit. The circuit configuration makes it possible to compensate undesirable propagation time differences between the digital signals.

Abstract: A monolithically integrated test circuit for testing a digital semiconductor circuit configuration that is formed on the same semiconductor chip and has a large number of elements to be tested. The test circuit has a test data pattern register for temporary storage of a test data pattern, a read and write circuit for writing and reading the data in the test data pattern register to and from the elements to be tested, and a comparison circuit. The comparison circuit tests for any difference between the data written to and read from the elements to be tested. The test circuit has a pattern variation circuit, which can be activated by an activation signal and varies the test data pattern from the test data pattern register before writing into the elements to be tested.

Abstract: An apparatus for function testing of electronic circuits includes a tester array having a terminal. A test circuit has at least two resistor elements, a common circuit node connected to the resistor elements for connection to the terminal of the tester array, and terminals of the resistor elements each being remote from the circuit node for connection to a respective output of an electronic circuit to be tested. A testing method for function testing of electronic circuits with such an apparatus includes placing the electronic circuit into a state in which signals are present at an output of the electronic circuit to be tested. The electronic circuit is function tested with respect to a resultant signal being established at the common circuit node.

Abstract: An integrated semiconductor circuit includes a semiconductor substrate. A number of first potential buses carry a first supply potential of the semiconductor circuit during operation. A number of second potential buses carry a second supply potential of the semiconductor circuit during operation. A number of circuit portions formed on the substrate are each connected between one of the first and one of the second potential buses for being supplied with electrical voltage. Connection points are formed on the substrate and are each assigned to one of the circuit portions for receiving an input or output signal for the circuit portion during operation of the circuit portion. Protective circuits are formed on the substrate and are each assigned to one of the circuit portions for preventing overvoltage. The protective circuits each have an input side connected to one of the connection points and an output side connected to the circuit portion.

Abstract: A semiconductor component includes a semiconductor body having a terminal pad, a semiconductor function element, and an electrically conductive connecting line connecting the terminal pad to the semiconductor function element. A protective element for protecting against electrostatic discharge is connected between the terminal pad and the semiconductor function element. A first supply line for a first supply potential is connected to the semiconductor function element. A second supply line for the first supply potential is connected to the protective element and is electrically conductively connected to the first supply line. A clamp element is connected to the connecting line and to the first supply line, for limiting a voltage applied to the clamp element to a clamp value.

Abstract: Integrated digital MOS-semiconductor circuit, including a first circuit part for generating charging and switching pulses, a second circuit part having an input connected to the first circuit part for being addressed by the pulses supplied by the first circuit part, first, second and third self-locking MOS-field effect transistors each having a source, a drain and a gate electrode, first and second capacitors having first and second terminals, the first terminal of the first capacitor being connected through the first transistor to the input of the second circuit part, the first terminal of the second capacitor being connected through the second transistor to the input of the second circuit part, a first supply potential source at reference potential, a second supply potential source different from reference potential being connected to at least one terminal of the third transistor and through the third transistor to the first terminal of the second capacitor, the second supply potential source also being con