Abstract: A circuit configuration for the identification of integrated semiconductor circuitries includes n programmable elements each having an output. A parallel-serial shift register has n parallel inputs each being connected to a respective one of the outputs of the n programmable elements, a data output, a control input for transferring electrical states of the programmable elements into the parallel-serial shift register, and a clock input for controlling a shift function of the parallel-serial shift register as a function of a clock signal to be applied to the clock input.

Abstract: The length of a column of a gaseous or liquid substance or of a solid bar is determined by generating a standing wave of known frequency, wavelength and/or wave velocity in the column or in the bar. The wave frequency is varied until at least two consecutive maxima (antinodes), two consecutive minima (nodes) or a minimum following a maximum of the amplitude of the standing wave have been detected. The length of the column of medium at known frequency and wave velocity of the standing wave generated in that column is computed from the equationL=c/[2(f.sub.n -f.sub.n-1)] (1),where L is the length of the column of medium, c is the wave velocity, f.sub.n is the frequency of the nth maximum and f.sub.n-1 the frequency of the (n-1)th maximum. Apparatus for implementing the method comprises a loudspeaker 1 mounted in a resonance chamber 2 with a tubular acoustic exit aperture 3.

Abstract: Integrated circuit having anti latch-up circuit in complementary MOS circuit technology. Due to the incorporation of non-linear elements between the ground (V.sub.ss) and the p-conductive semiconductor substrate (P.sub.sub) and between the supply voltage (V.sub.DD) and the n-conductive semiconductor zone (N.sub.w), the risk of the occurrence of the latch-up effect triggered by the build-up of base charges at the parasitic vertical and lateral bipolar transistors is diminished. The space requirement for the non-linear elements to be additionally incorporated is low and the circuit properties of the MOS transistors are not influenced as a result thereof. The realization of the non-linear elements can ensue with Schottky contacts or with additional MOS transistors that are wired as diode elements. A realization in the form of buried diodes of polycrystalline silicon (PSi) is also possible, realized, for example, as barrier layer diodes.

Abstract: An integrated circuit configuration includes a configuration circuit with a potential lead and a connection device for a control potential. An electronic circuit connects the connection device to the potential lead.

Abstract: The length of a column of a gaseous or liquid substance or of a solid bar is determined by generating a standing wave of known frequency, wavelength and/or wave velocity in the column or in the bar. The wave frequency is varied until at least two consecutive maxima (antinodes), two consecutive minima (nodes) or a minimum following a maximum of the amplitude of the standing wave have been detected. The length of the column of medium at known frequency and wave velocity of the standing wave generated in that column is computed from the equationL=c/[2(f.sub.n -f.sub.n-1)] (1),where L is the length of the column of medium, C is the wave velocity, F.sub.n is the frequency of the nth maximum and F.sub.n-1 the frequency of the (n-1)th maximum. Apparatus for implementing the method comprises a loudspeaker 1 mounted in a resonance chamber 2 with a tubular acoustic exit aperture 3.

Abstract: A circuit configuration for compensating for noise signals occurring in a component circuit of an integrated semiconductor circuit includes a sensor circuit for detecting and converting noise signals that occur. A converter circuit is connected to the sensor circuit for preparing and converting the detected noise signals into logic levels. A control element is connected between the converter circuit and the component circuit for controlling the flow of current in the component circuit.

Abstract: The risk of a latch-up is diminished by the incorporation of an additional bypass transistor between the output (OUT) and the supply voltage (V.sub.DD) of an integrated circuit, for example a CMOS output stage. In case positive over-voltages that are greater than the sum of the supply voltage (V.sub.DD) and the conducting-state voltage of the bypass transistor occur at the output (OUT), the bypass transistor becomes conductive and represents a low-impedance connection between the output (OUT) and the supply voltage (V.sub.DD). In this case, the bypass transistor (BT) suctions additional charge carriers off and thereby increases the trigger current needed for the appearance of latch-up. The incorporation of an additional bypases transistor is possible both given well-shaped semiconductor zones that lie at a fixed potential as well as given well-shaped semiconductor zones that are wired to a variable potential. FIG.

Abstract: A circuit configuration for the identification of integrated semiconductor circuitries includes n programmable elements. A common line is connected to the programmable elements. An n-stage serial-parallel shift register has a data input, n parallel outputs, and a clock input for controlling a shift function of the serial-parallel shift register as a function of a clock signal to be applied to the clock input. Transistors each have a drain connected to a respective one of the programmable elements, a source connected to a supply potential, and a gate connected to a respective one of the parallel outputs of the serial-parallel shift register. Instead of n-stage serial-parallel shift register, it is also possible to use a clocked n-stage oscillator, such as a ring oscillator, or an n-stage counter, such as ring counter.

Abstract: A synchronizing flip-flop circuit configuration for synchronizing data includes an input and an output of the synchronizing flip-flop circuit configuration. A first transfer gate, connected to the input of the synchronizing flip-flop circuit configuration, is controlled by a first clock signal. A second transfer gate connected between the first transfer gate and the output of the synchronizing flip-flop circuit configuration is controlled by a second clock signal being inverted with respect to the first clock signal. A first series-connected inverter pair is connected between the first transfer gate and the output of the synchronizing flip-flop circuit configuration. At least one second inverter series-connected inverter pair is connected in series with the first inverter configuration between the first transfer gate and the output of the synchronizing flip-flop circuit configuration, thereby preventing occurrence of meta-stable conditions between data to be synchronized.

Abstract: A latch-up protection circuit for an integrated circuit using complementary MOS circuit technology has a substrate bias generator that applies a negative substrate bias to a semiconductor substrate having a p-conductive material into which a well-shaped semiconductor zone of n-conductive material is inserted. In order to avoid latch-up effects in the integrated circuit, an electronic protection circuit interrupts the capacitive charging currents of a capacitor in the substrate depending on the potential of the semiconductor substrate which is taken at a doped substrate bias terminal. The electronic protection circuit disconnects a capacitor bias generator from the capacitor when a voltage on the substrate bias terminal is greater than a difference between a reference potential and a threshold voltage of a first transistor in the electronic protection circuit.