Abstract: Various techniques are provided to implement programmable linear-feedback shift register (LFSR) circuits. In one example, the LFSR circuit includes state storage elements. Each state storage element is configured to store a state signal. The LFSR circuit further includes programmable logic stage circuits each configured to selectively receive an input signal and a set of state signals, determine an output signal based at least on the set of state signals, and provide the output signal. Each programmable logic stage circuit is connected to at least one other programmable logic stage circuit. The LFSR circuit further includes pipeline elements. Each pipeline element is configured to selectively connect at least two programmable logic stage circuits. The LFSR circuit further includes sets of latency balance elements. Related systems and methods are provided.

Abstract: Various techniques are provided to implement programmable linear-feedback shift register (LFSR) circuits. In one example, the LFSR circuit includes state storage elements. Each state storage element is configured to store a state signal. The LFSR circuit further includes programmable logic stage circuits each configured to selectively receive an input signal and a set of state signals, determine an output signal based at least on the set of state signals, and provide the output signal. Each programmable logic stage circuit is connected to at least one other programmable logic stage circuit. The LFSR circuit further includes pipeline elements. Each pipeline element is configured to selectively connect at least two programmable logic stage circuits. The LFSR circuit further includes sets of latency balance elements. Related systems and methods are provided.

Abstract: Various techniques are provided to implement programmable linear-feedback shift register (LFSR) circuits. In one example, the LFSR circuit includes state storage elements. Each state storage element is configured to store a state signal. The LFSR circuit further includes programmable logic stage circuits each configured to selectively receive an input signal and a set of state signals, determine an output signal based at least on the set of state signals, and provide the output signal. Each programmable logic stage circuit is connected to at least one other programmable logic stage circuit. The LFSR circuit further includes pipeline elements. Each pipeline element is configured to selectively connect at least two programmable logic stage circuits. The LFSR circuit further includes sets of latency balance elements. Related systems and methods are provided.

Abstract: Disclosed aspects relate to methods and apparatus for coexistent radio frequency (RF) systems in a wireless device. Control of a wireless device includes detecting when a turn on signal is issued to a first radio system, and then controlling the second radio system to either modify the operation of receiver circuitry in the second radio system to protect components within that system, or modify transmit circuitry to stop transmissions for protecting components within one radio system potentially affected by transmission from the other radio system in the wireless device. Disclosed also is monitoring of transmission states of the radio systems based on reading messages between the first and second radio systems and issuing a notification message based thereon such that one of the radio systems may suspend monitoring of a transmit channel for permission to transmit in order to reduce power consumption due to such monitoring of the channel.

Abstract: Disclosed aspects relate to methods and apparatus for coexistent radio frequency (RF) systems in a wireless device. Control of a wireless device includes detecting when a turn on signal is issued to a first radio system, and then controlling the second radio system to either modify the operation of receiver circuitry in the second radio system to protect components within that system, or modify transmit circuitry to stop transmissions for protecting components within one radio system potentially affected by transmission from the other radio system in the wireless device. Disclosed also is monitoring of transmission states of the radio systems based on reading messages between the first and second radio systems and issuing a notification message based thereon such that one of the radio systems may suspend monitoring of a transmit channel for permission to transmit in order to reduce power consumption due to such monitoring of the channel.

Abstract: Disclosed aspects relate to methods and apparatus for coexistent radio frequency (RF) systems in a wireless device. Control of a wireless device includes detecting when a turn on signal is issued to a first radio system, and then controlling the second radio system to either modify the operation of receiver circuitry in the second radio system to protect components within that system, or modify transmit circuitry to stop transmissions for protecting components within one radio system potentially affected by transmission from the other radio system in the wireless device. Disclosed also is monitoring of transmission states of the radio systems based on reading messages between the first and second radio systems and issuing a notification message based thereon such that one of the radio systems may suspend monitoring of a transmit channel for permission to transmit in order to reduce power consumption due to such monitoring of the channel.

Abstract: Systems, methods, and apparatus for data communication are provided. A method performed by a bus master includes terminating transmission of a first datagram by signaling a first bus park cycle on a serial bus, causing a driver to enter a high-impedance state, opening an interrupt window by providing a first edge in a clock signal transmitted on a second line of the serial bus, closing the interrupt window by providing a second edge in the clock signal, signaling a second bus park cycle on the serial bus, initiating an arbitration process when an interrupt was received on the first line of the serial bus while the interrupt window was open, and initiating a transmission of a second datagram when an interrupt was not received on the first line of the serial bus while the interrupt window was open.

Abstract: Systems, methods, and apparatus for sharing a serial bus interface among devices having different operating speeds are described. A sequence of commands on a data line of the serial bus are generated including a start condition signal and a device identifier signal where the identifier signal is part of a command frame in the sequence of commands. The sequence of commands is transmitted on the data line concurrent with the transmission of a clock signal on a clock line of the serial bus during the duration of the device identifier signal. The frequency of the clock signal is set at a first clock frequency for the duration of the device identifier signal where the first clock frequency is a frequency supported among all devices coupled to the serial bus, allowing all devices to decode an initial sequence, whether the devices are configured for higher frequency operation or not.

Abstract: Systems, methods, and apparatus for data communication are provided. A method performed by a bus master includes terminating transmission of a first datagram by signaling a first bus park cycle on a serial bus, causing a driver to enter a high-impedance state, opening an interrupt window by providing a first edge in a clock signal transmitted on a second line of the serial bus, closing the interrupt window by providing a second edge in the clock signal, signaling a second bus park cycle on the serial bus, initiating an arbitration process when an interrupt was received on the first line of the serial bus while the interrupt window was open, and initiating a transmission of a second datagram when an interrupt was not received on the first line of the serial bus while the interrupt window was open.

Abstract: Disclosed aspects relate to methods and apparatus for coexistent radio frequency (RF) systems in a wireless device. Control of a wireless device includes detecting when a turn on signal is issued to a first radio system, and then controlling the second radio system to either modify the operation of receiver circuitry in the second radio system to protect components within that system, or modify transmit circuitry to stop transmissions for protecting components within one radio system potentially affected by transmission from the other radio system in the wireless device. Disclosed also is monitoring of transmission states of the radio systems based on reading messages between the first and second radio systems and issuing a notification message based thereon such that one of the radio systems may suspend monitoring of a transmit channel for permission to transmit in order to reduce power consumption due to such monitoring of the channel.

Abstract: Methods and apparatuses are described that facilitate data communication between a first slave device and a second slave device across a serial bus interface. In one configuration, a master device receives, from a first slave device, a request to send a masked-write datagram to a second slave device via a bus, wherein the masked-write datagram is addressed to a radio frequency front end (RFFE) register of the second slave device. The masked-write datagram includes a mask field identifying at least one bit to be changed in the RFFE register and a data field providing a value of the at least one bit to be changed in the RFFE register. The master device detects whether the first slave device is authorized to send the masked-write datagram to the second slave device and permits the first slave device to send the masked-write datagram to the second slave device if authorization is detected.

Abstract: Methods and apparatuses are described that facilitate data communication between a first slave device and a second slave device across a serial bus interface. In one configuration, a master device receives, from a first slave device, a request to send a masked-write datagram to a second slave device via a bus, wherein the masked-write datagram is addressed to a radio frequency front end (RFFE) register of the second slave device. The masked-write datagram includes a mask field identifying at least one bit to be changed in the RFFE register and a data field providing a value of the at least one bit to be changed in the RFFE register. The master device detects whether the first slave device is authorized to send the masked-write datagram to the second slave device and permits the first slave device to send the masked-write datagram to the second slave device if authorization is detected.

Abstract: A method, an apparatus, and a computer program product for data communication are provided. The method may include providing a plurality of data channels on a communications link, determining unused bandwidth as a difference between total bandwidth provided by the communications link and bandwidth used by the plurality of data channels, allocating the unused bandwidth to a virtual channel, scheduling the plurality of data channels and the virtual channel in accordance with a time-based multiplexing scheme, and disabling interface circuitry used to couple the transmitter to the communications link when the virtual channel is scheduled. Each of the plurality of data channels may be assigned to a source of data to be transmitted on the communications link.

Abstract: Methods and apparatuses are described that facilitate the communication of data between a transmitter and a receiver across a serial bus interface. In one configuration, a transmitter generates a datagram based on a register address, detects whether the register address is within a high data rate (HDR) access address range, and sends a payload of the datagram to the receiver according to a HDR mode when the register address is within the HDR access address range. In another configuration, the transmitter generates a datagram including at least a command field and a data field, sends the command field to the receiver according to a single data rate (SDR) mode, wherein the command field indicates a transition to a high data rate (HDR) mode for sending the data field, and sends the data field to the receiver according to the HDR mode.

Abstract: Methods and apparatuses are described that facilitate the communication of data between a transmitter and a receiver across a serial bus interface. In one configuration, a transmitter generates a datagram based on a 16-bit address and a mask-and-data pair burst length, the 16-bit address including a most significant byte (MSB) and a least significant byte (LSB), compares the MSB to a receiver base address maintained in a shadow register, compares the mask-and-data pair burst length to a receiver masked-write burst length maintained in the shadow register, and sends the datagram to the receiver via the bus interface when: the MSB is equal to the receiver base address maintained in the shadow register, and the mask-and-data pair burst length is equal to the receiver masked-write burst length maintained in the shadow register.

Abstract: A method, an apparatus, and a computer program product for data communication are provided. The method may include providing a plurality of data channels on a communications link, determining unused bandwidth as a difference between total bandwidth provided by the communications link and bandwidth used by the plurality of data channels, allocating the unused bandwidth to a virtual channel, scheduling the plurality of data channels and the virtual channel in accordance with a time-based multiplexing scheme, and disabling interface circuitry used to couple the transmitter to the communications link when the virtual channel is scheduled. Each of the plurality of data channels may be assigned to a source of data to be transmitted on the communications link.

Abstract: A method, an apparatus, and a computer program product for data communication are provided. The method may include providing a frame of encoded data, generating a synchronization symbol to precede the encoded data when the frame is transmitted over a communication link, the synchronization symbol providing an identification of a type of the frame in accordance with an encoding scheme. The synchronization symbol may be encoded using a redundant coding scheme to support error correction for the identification of the type of frame. The frame may have a predefined fixed length.

Abstract: A dither unit with a programmable kernel matrix in which each indexed location/entry may store one or more dither values. Each dither value in a respective entry of the kernel matrix may correspond to the number of bits that are truncated during dithering. During dithering of each pixel of an image, entries in the kernel matrix may be indexed according to the relative coordinates of the pixel within the image. A dither value for the pixel may be selected from the indexed entry based on the truncated least significant bits of the pixel component value. When the kernel matrix is storing more than one dither value per entry, the dither value may be selected based further on the number of truncated least significant bits. A dithered pixel component value may then be generated according to the dither value and the remaining most significant bits of the pixel component value.

Abstract: In an embodiment, a display apparatus includes multiple physical interface circuits (PHYs) couple to respective displays. In a mirror mode, the PHYs may operate as masters. A primary master PHY may control a synchronization interface to one or more secondary master PHYs. The synchronization interface may include a start of frame signal that the primary master PHY may generate to indicate the beginning of a new frame. The secondary master PHYs may be configured to generate internal start of frame signals while independently processing the same display data as the primary master. If the internally-generated start of frame and the received start of frame occur within a window of tolerance of each other, then the secondary masters may continue to process the display data stream independently. A secondary master that detects the start of frames occur outside of the window of tolerance may resynchronize.

Abstract: In an embodiment, a display apparatus includes multiple physical interface circuits (PHYs) couple to respective displays. In a mirror mode, the PHYs may operate as masters. A primary master PHY may control a synchronization interface to one or more secondary master PHYs. The synchronization interface may include a start of frame signal that the primary master PHY may generate to indicate the beginning of a new frame. The secondary master PHYs may be configured to generate internal start of frame signals while independently processing the same display data as the primary master. If the internally-generated start of frame and the received start of frame occur within a window of tolerance of each other, then the secondary masters may continue to process the display data stream independently. A secondary master that detects the start of frames occur outside of the window of tolerance may resynchronize.