Patents by Inventor Wolfgang Schnitt
Wolfgang Schnitt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240128314Abstract: A semiconductor power device and a method for manufacturing the same is provided. The semiconductor power device includes a semiconductor body including a conductive substrate and an epitaxial layer of a first charge type grown on the conductive substrate, and one or more inner wells of a second charge type different from the first charge type in an active area of the semiconductor power device. At least some of the one or more inner wells of the second charge type are formed using at least two ion implantation steps. One step is dedicated to forming the inner wells of the second type whereas one or more further ion implantation steps are simultaneously used for forming a respective JTE structure and for increasing a dopant concentration of at least one well of the second charge type.Type: ApplicationFiled: October 17, 2023Publication date: April 18, 2024Applicant: NEXPERIA B.V.Inventors: Sönke Habenicht, Massimo Cataldo Mazzillo, Georgio El-Zammar, Jesus Roberto Urresti Ibanez, Wolfgang Schnitt
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Publication number: 20230290889Abstract: A semiconductor product, including: a base region doped with a first conductivity type; a plurality of stripe regions doped with a second conductivity type, provided on an upper surface of the base region, and the second conductivity type is different from the first conductivity type; a plurality of cell regions doped with the second conductivity type, provided on the upper surface of the base region; and a metal layer arranged on the upper surface of the base region, so that the metal layer defines a Schottky barrier with the base region and covers the plurality of stripe regions and the plurality of cell regions; and each cell region of a majority of the plurality of cell regions contacts at least one neighboring stripe region of the plurality of stripe regions and the stripe regions and the cell regions extend into the base region to different depths.Type: ApplicationFiled: March 8, 2023Publication date: September 14, 2023Applicant: NEXPERIA B.V.Inventors: Massimo Cataldo Mazzillo, Sönke Habenicht, Joachim Stache, Wolfgang Schnitt, Jesus Roberto Ibanez Urresti
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Publication number: 20230230892Abstract: A semiconductor device such as a chip-scale package is provided. Aspects of the present disclosure further relate to a method for manufacturing such a device. According to an aspect of the present disclosure, a semiconductor device is provided that includes a conformal coating arranged on its sidewalls and on the perimeter part of the semiconductor die of the semiconductor device. To prevent the conformal coating from covering unwanted areas, such as electrical terminals, a sacrificial layer is arranged prior to arranging the conformal coating. By removing the sacrificial layer, the conformal coating can be removed locally. The conformal coating covers the perimeter part of the semiconductor die by the semiconductor device, in which part a remainder of a sawing line or dicing street is provided.Type: ApplicationFiled: January 17, 2023Publication date: July 20, 2023Applicant: NEXPERIA B.V.Inventors: Regnerus Hermannus Poelma, Hartmut Bünning, Stefan Berglund, Hans-Juergen Funke, Johannes Josinus Kuipers, Joep Stokkermans, Wolfgang Schnitt
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Publication number: 20230223396Abstract: This disclosure relates to a semiconductor device including a device with high clamping voltage (HVC device), and an OTS device. Such a semiconductor device provides very advantageous ESD protection. The semiconductor device can be realized in two ways: an OTS device and a device with high clamping voltage can be realized as discrete, independent devices that are combined in one semiconductor package, or an OTS device can be integrated into interconnect layers of a device with high clamping voltage by integration.Type: ApplicationFiled: December 29, 2022Publication date: July 13, 2023Applicant: NEXPERIA B.V.Inventors: Joachim Utzig, Steffen Holland, Wolfgang Schnitt, Hans-Martin Ritter
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Publication number: 20230060216Abstract: The present disclosure relates to a wide band-gap merged p-i-n/Schottky, MPS, diode, and to a method of manufacturing the same. The present disclosure particularly relates to Silicon Carbide, SiC, MPS diodes. According to the present disclosure, the MPS diode includes different Schottky contacts with different IV characteristics, and/or ohmic contacts with a different contact resistance and/or threshold voltage. This allows the conduction area of the MPS diode to change more gradually with forward bias thereby avoiding drawbacks associated with a large conduction area when switching from a forward biasing mode to a reverse biasing mode. Therefore, the dynamic switching performance can be improved in a wide operation voltage range.Type: ApplicationFiled: August 25, 2022Publication date: March 2, 2023Applicant: NEXPERIA B.V.Inventors: Massimo Mazzillo, Joachim Stache, Surabhi Lodha, Wolfgang Schnitt
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Patent number: 11315847Abstract: The disclosure relates to chips scale packages and methods of forming such packages or an array of such packages. The semiconductor chip scale package comprises: a semiconductor die, comprising: a first major surface opposing a second major surface; a plurality side walls extending between the first major surface and the second major surface; a plurality of electrical contacts arranged on the second major surface of the semiconductor die; and an inorganic insulating material arranged on the plurality of side walls and on the first major surface.Type: GrantFiled: February 16, 2018Date of Patent: April 26, 2022Assignee: Nexperia B.V.Inventors: Wolfgang Schnitt, Tobias Sprogies
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Patent number: 10957685Abstract: A semiconductor device and method of manufacturing a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a semiconductor layer located on the substrate; at least one shallow trench and at least one deep trench. Each of the at least one shallow trench and the at least one deep trench extending from a first major surface of the semiconductor layer. Sidewall regions and base regions of the trenches comprise a doped trench region and the trenches are at least partially filled with a conductive material contacting the doped region. The shallow trenches terminate in the semiconductor layer and the deep trench terminates in the semiconductor substrate.Type: GrantFiled: October 18, 2018Date of Patent: March 23, 2021Assignee: Nexperia B.V.Inventors: Steffen Holland, Zhihao Pan, Jochen Wynants, Hans-Martin Ritter, Tobias Sprogies, Thomas Igel-Holtzendorff, Wolfgang Schnitt, Joachim Utzig
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Patent number: 10529644Abstract: A semiconductor device and a method of making the same. The device includes an electrically conductive heat sink having a first surface. The device also includes a semiconductor substrate. The device further includes a first contact located on a first surface of the substrate. The device also includes a second contact located on a second surface of the substrate. The first surface of the substrate is mounted on the first surface of the heat sink for electrical and thermal conduction between the heat sink and the substrate via the first contact. The second surface of the substrate is mountable on a surface of a carrier.Type: GrantFiled: February 22, 2016Date of Patent: January 7, 2020Assignee: Nexperia B.V.Inventors: Shun Tik Yeung, Pompeo Umali, Hans-Juergen Funke, Chi Ho Leung, Wolfgang Schnitt, Zhihao Pan
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Publication number: 20190123037Abstract: A semiconductor device and method of manufacturing a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a semiconductor layer located on the substrate; at least one shallow trench and at least one deep trench. Each of the at least one shallow trench and the at least one deep trench extending from a first major surface of the semiconductor layer. Sidewall regions and base regions of the trenches comprise a doped trench region and the trenches are at least partially filled with a conductive material contacting the doped region. The shallow trenches terminate in the semiconductor layer and the deep trench terminates in the semiconductor substrate.Type: ApplicationFiled: October 18, 2018Publication date: April 25, 2019Applicant: NEXPERIA B.V.Inventors: Steffen Holland, Zhihao Pan, Jochen Wynants, Hans-Martin Ritter, Tobias Sprogies, Thomas lgel-Holtzendorff, Wolfgang Schnitt, Joachim Utzig
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Publication number: 20180233426Abstract: The disclosure relates to chips scale packages and methods of forming such packages or an array of such packages. The semiconductor chip scale package comprises: a semiconductor die, comprising: a first major surface opposing a second major surface; a plurality side walls extending between the first major surface and the second major surface; a plurality of electrical contacts arranged on the second major surface of the semiconductor die; and an inorganic insulating material arranged on the plurality of side walls and on the first major surface.Type: ApplicationFiled: February 16, 2018Publication date: August 16, 2018Applicant: NEXPERIA B.V.Inventors: Wolfgang Schnitt, Tobias Sprogies
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Patent number: 9806034Abstract: A method of protecting sidewalls a plurality of semiconductor devices is disclosed. The method includes fabricating the plurality of semiconductor devices on a semiconductor wafer, etching to form a trench grid network on the backside of the semiconductor wafer. The trench grid network demarcate physical boundaries of each of the plurality of semiconductor devices. The method also includes depositing a protective layer on the backside and etching to remove the protective layer from horizontal surfaces and to singulate each of the plurality of semiconductor devices from the semiconductor wafer.Type: GrantFiled: June 16, 2016Date of Patent: October 31, 2017Assignee: Nexperia B.V.Inventors: Hans-Juergen Funke, Tobias Sprogies, Rolf Brenner, Rüdiger Weber, Wolfgang Schnitt, Frank Burmeister
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Publication number: 20160260651Abstract: A semiconductor device and a method of making the same. The device includes an electrically conductive heat sink having a first surface. The device also includes a semiconductor substrate. The device further includes a first contact located on a first surface of the substrate. The device also includes a second contact located on a second surface of the substrate. The first surface of the substrate is mounted on the first surface of the heat sink for electrical and thermal conduction between the heat sink and the substrate via the first contact. The second surface of the substrate is mountable on a surface of a carrier.Type: ApplicationFiled: February 22, 2016Publication date: September 8, 2016Inventors: Shun Tik YEUNG, Pompeo Umali, Hans-Juergen Funke, Chi Ho Leung, Wolfgang Schnitt, Zhihao Pan
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Patent number: 9368963Abstract: An ESD protection circuit comprises a series connection of at least two protection components between a signal line to be protected and a return line (e.g. ground), comprising a first protection component connected to the signal line and a second protection component connected to the ground line. They are connected with opposite polarity so that when one conducts in forward direction the other conducts in reverse breakdown mode. A bias voltage source connects to the junction between the two protection components through a bias impedance. The use of the bias voltage enables the signal distortions resulting from the ESD protection circuit to be reduced.Type: GrantFiled: November 5, 2013Date of Patent: June 14, 2016Assignee: NXP B.V.Inventors: Klaus Reimann, Hans-Martin Ritter, Wolfgang Schnitt, Anco Heringa
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Patent number: 8853859Abstract: Aspects of the disclosure are directed towards an efficient wafer level chip-scale package, and methods or producing the packages. Various aspects are directed to protecting against humidity, contamination, mechanical damage, and current leakage while maintaining isolation and manufacturability of the plastic package and a ratio of active die size to package size.Type: GrantFiled: May 4, 2012Date of Patent: October 7, 2014Assignee: NXP B.V.Inventors: Olaf Pfenningstorf, Wolfgang Schnitt
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Publication number: 20140160607Abstract: An ESD protection circuit comprises a series connection of at least two protection components between a signal line to be protected and a return line (e.g. ground), comprising a first protection component connected to the signal line and a second protection component connected to the ground line. They are connected with opposite polarity so that when one conducts in forward direction the other conducts in reverse breakdown mode. A bias voltage source connects to the junction between the two protection components through a bias impedance. The use of the bias voltage enables the signal distortions resulting from the ESD protection circuit to be reduced.Type: ApplicationFiled: November 5, 2013Publication date: June 12, 2014Applicant: NXP B.V.Inventors: Klaus REIMANN, Hans-Martin RITTER, Wolfgang Schnitt, Anco HERINGA
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Patent number: 8711532Abstract: In one embodiment, an integrated circuit, and method of manufacturing thereof, is provided. The integrated circuit contains an over-voltage protection element and an over-current protection element. The integrated circuit operates to provide enhanced and efficient ESD functionality. The over-current element of the instant disclosure includes a diffusion protection layer to enhance the lifetime of the over-current element and improve functionality.Type: GrantFiled: August 24, 2011Date of Patent: April 29, 2014Assignee: NXP, B.V.Inventors: Olaf Pfennigstorf, Wolfgang Schnitt
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Publication number: 20130292837Abstract: Aspects of the disclosure are directed towards an efficient wafer level chip-scale package, and methods or producing the packages. Various aspects are directed to protecting against humidity, contamination, mechanical damage, and current leakage while maintaining isolation and manufacturability of the plastic package and a ratio of active die size to package size.Type: ApplicationFiled: May 4, 2012Publication date: November 7, 2013Inventors: Olaf Pfennigstorf, Wolfgang Schnitt
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Publication number: 20130050883Abstract: In one embodiment, an integrated circuit, and method of manufacturing thereof, is provided. The integrated circuit contains an over-voltage protection element and an over-current protection element. The integrated circuit operates to provide enhanced and efficient ESD functionality. The over-current element of the instant disclosure includes a diffusion protection layer to enhance the lifetime of the over-current element and improve functionality.Type: ApplicationFiled: August 24, 2011Publication date: February 28, 2013Inventors: Olaf Pfennigstorf, Wolfgang Schnitt
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Patent number: 8338228Abstract: In order to provide a method of detaching a thin semiconductor circuit (1) from its base (2), wherein the semiconductor circuit (1) is provided with terminals (3) for electrical contacting, in particular with gold contacts, by means of which method thin semiconductor circuits (1) can also be mounted without damage for example directly on a chip card, it is proposed that a layer of soldering tin (6) is applied to a support substrate (4), the support substrate (4) is soldered to the electrical terminals (3) and the base (2) of the semiconductor circuit (1) is removed.Type: GrantFiled: August 9, 2005Date of Patent: December 25, 2012Assignee: NXP B.V.Inventors: Andreas Gakis, Wolfgang Schnitt
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Patent number: 8159032Abstract: The electronic device comprises an ESD device (20) for protection against electrostatic discharge and provided with suitable protection elements (22) in combination with an integrated circuit (10). The integrated circuit (10) is particularly a so-called bridging circuit or driver circuit for external devices such as SIM cards, memory sticks, USB busses or 12C busses. The ESD device (20) is provided with a chip scale package in that the bumps (40) can be placed on a printed circuit board directly. The integrated circuit (10) is stacked on the ESD device (20).Type: GrantFiled: July 6, 2005Date of Patent: April 17, 2012Assignee: NXP B.V.Inventors: Wolfgang Schnitt, Kai Neumann, Michael Joehren