Patents by Inventor Wolfgang Soldner
Wolfgang Soldner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9478979Abstract: In an embodiment, an electrostatic discharge (ESD) circuit for providing protection between a first node and a second node includes a first MOS device having a first source/drain coupled to a first node, and a second source/drain coupled to an intermediate node. The ESD circuit also includes a first capacitor coupled between a gate of the first MOS device and the first node, a first resistor coupled between the gate of the first MOS device the intermediate node, a second MOS device having a first source/drain coupled to the intermediate node, and a second source/drain coupled to the second node, a second capacitor coupled between a gate of the second MOS device and the first node, and a second resistor coupled between the gate of the second MOS device and the second node.Type: GrantFiled: April 20, 2015Date of Patent: October 25, 2016Assignee: Infineon Technologies AGInventors: Krzysztof Domanski, Wolfgang Soldner, Cornelius Christian Russ, David Alvarez, Adrien Ille
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Patent number: 9197061Abstract: Techniques and architectures corresponding to electrostatic discharge clamping circuits with tracing circuitry are described.Type: GrantFiled: December 21, 2010Date of Patent: November 24, 2015Assignee: INFINEON TECHNOLOGIES AGInventors: Christian Russ, Wolfgang Soldner, Klaus von Arnim, David Alvarez, Krzysztof Domanski, Gernot Langguth
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Publication number: 20150229126Abstract: In an embodiment, an electrostatic discharge (ESD) circuit for providing protection between a first node and a second node includes a first MOS device having a first source/drain coupled to a first node, and a second source/drain coupled to an intermediate node. The ESD circuit also includes a first capacitor coupled between a gate of the first MOS device and the first node, a first resistor coupled between the gate of the first MOS device the intermediate node, a second MOS device having a first source/drain coupled to the intermediate node, and a second source/drain coupled to the second node, a second capacitor coupled between a gate of the second MOS device and the first node, and a second resistor coupled between the gate of the second MOS device and the second node.Type: ApplicationFiled: April 20, 2015Publication date: August 13, 2015Inventors: Krzysztof Domanski, Wolfgang Soldner, Cornelius Christian Russ, David Alvarez, Adrien Ille
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Patent number: 9013842Abstract: In an embodiment, an electrostatic discharge (ESD) circuit for providing protection between a first node and a second node includes a first MOS device having a first source/drain coupled to a first node, and a second source/drain coupled to an intermediate node. The ESD circuit also includes a first capacitor coupled between a gate of the first MOS device and the first node, a first resistor coupled between the gate of the first MOS device the intermediate node, a second MOS device having a first source/drain coupled to the intermediate node, and a second source/drain coupled to the second node, a second capacitor coupled between a gate of the second MOS device and the first node, and a second resistor coupled between the gate of the second MOS device and the second node.Type: GrantFiled: January 10, 2011Date of Patent: April 21, 2015Assignee: Infineon Technologies AGInventors: Krzysztof Domanski, Wolfgang Soldner, Cornelius Christian Russ, David Alvarez, Adrien Ille
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Patent number: 8976496Abstract: Techniques and architectures corresponding to electrostatic discharge blocking circuits are described.Type: GrantFiled: December 21, 2010Date of Patent: March 10, 2015Assignee: Infineon Technologies AGInventors: Christian Russ, Wolfgang Soldner, Gernot Langguth, David Alvarez, Krzysztof Domanski, Klaus von Arnim
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Patent number: 8531807Abstract: Embodiments of this disclosure relate to electrostatic discharge (ESD) protection techniques. For example, some embodiments include a variable resistor that selectively shunts power of an incoming ESD pulse from a first circuit node to a second circuit node and away from a semiconductor device. A control voltage provided to the variable resistor causes the transistor to change between a fully-off mode where only sub-threshold current, if any, flows; a fully-on mode wherein a maximum amount of current flows; and an analog mode wherein an intermediate and time-varying amount of current flows. In particular, the analog mode allows the ESD protection device to shunt power more precisely than previously achievable, such that the ESD protection device can protect semiconductor devices from ESD pulses.Type: GrantFiled: November 14, 2012Date of Patent: September 10, 2013Assignee: Infineon Technologies AGInventors: Wolfgang Soldner, Gernot Langguth, Christian Russ, Harald Gossner
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Patent number: 8456785Abstract: An embodiment semiconductor device has a first device region disposed on a second device region within an ESD device region disposed within a semiconductor body. Also included is a third device region disposed on the second device region, a fourth device region adjacent to the second device region, a fifth device region disposed within the fourth device region, and a sixth device region adjacent to the fourth device region. The first and fourth regions have a first semiconductor type, and the second, third, fifth and sixth regions have a second conductivity type opposite the first conductivity type. An interface between the fourth device region and the sixth device region forms a diode junction. The first, second, fourth and fifth device regions form a silicon controlled rectifier.Type: GrantFiled: October 25, 2010Date of Patent: June 4, 2013Assignee: Infineon Technologies AGInventors: Krzysztof Domanski, Cornelius Christian Russ, David Alvarez, Wolfgang Soldner
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Patent number: 8390970Abstract: A method and a system for ESD protection are provided. In one embodiment, the system comprises a circuit comprising at least one non-linear element, an application module configured to apply a set of current pulses to the circuit, a determination module configured to determine at least one frequency-dependent and amplitude-dependent transfer function of the circuit based on the set of applied current pulses, a modeling module configured to model at least one frequency-dependent and current-dependent impedance of the at least one non-linear element, and a simulation module to simulate a transmission to the circuit based on the model.Type: GrantFiled: October 27, 2010Date of Patent: March 5, 2013Assignee: Infineon Technologies AGInventors: Harald Gossner, David Johnsson, Wolfgang Soldner
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Patent number: 8335064Abstract: Embodiments of this disclosure relate to electrostatic discharge (ESD) protection techniques. For example, some embodiments include a variable resistor that selectively shunts power of an incoming ESD pulse from a first circuit node to a second circuit node and away from a semiconductor device. A control voltage provided to the variable resistor causes the transistor to change between a fully-off mode where only sub-threshold current, if any, flows; a fully-on mode wherein a maximum amount of current flows; and an analog mode wherein an intermediate and time-varying amount of current flows. In particular, the analog mode allows the ESD protection device to shunt power more precisely than previously achievable, such that the ESD protection device can protect semiconductor devices from ESD pulses.Type: GrantFiled: June 30, 2010Date of Patent: December 18, 2012Assignee: Infineon Technologies AGInventors: Wolfgang Soldner, Gernot Langguth, Christian Russ, Harald Gossner
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Patent number: 8315024Abstract: Implementations are presented herein that include an electrostatic discharge (ESD) protection circuit. The ESD protection circuit includes a first transistor and a second transistor. The first transistor has a first terminal that is coupled to a first supply line and a bulk that is coupled to a second supply line. The second transistor has a first terminal that is coupled to the second supply line, a bulk that is coupled to the first supply line and a second terminal that is coupled to a second terminal of the first transistor to define a protected node. The ESD protection circuit further includes a current limiting element that has a first terminal that is coupled to the protected node.Type: GrantFiled: September 16, 2009Date of Patent: November 20, 2012Assignee: Infineon Technologies AGInventors: Christian Russ, Wolfgang Soldner, Gernot Langguth, David Alvarez, Krysztof Domanski
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Publication number: 20120176710Abstract: In an embodiment, an electrostatic discharge (ESD) circuit for providing protection between a first node and a second node includes a first MOS device having a first source/drain coupled to a first node, and a second source/drain coupled to an intermediate node. The ESD circuit also includes a first capacitor coupled between a gate of the first MOS device and the first node, a first resistor coupled between the gate of the first MOS device the intermediate node, a second MOS device having a first source/drain coupled to the intermediate node, and a second source/drain coupled to the second node, a second capacitor coupled between a gate of the second MOS device and the first node, and a second resistor coupled between the gate of the second MOS device and the second node.Type: ApplicationFiled: January 10, 2011Publication date: July 12, 2012Inventors: Krzysztof Domanski, Wolfgang Soldner, Cornelius Christian Russ, David Alvarez, Adrien Ille
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Publication number: 20120154962Abstract: Techniques and architectures corresponding to electrostatic discharge clamping circuits with tracing circuitry are described.Type: ApplicationFiled: December 21, 2010Publication date: June 21, 2012Applicant: Infineon Technologies AGInventors: Christian Russ, Wolfgang Soldner, Klaus von Arnim, David Alvarez, Krzysztof Domanski, Gernot Langguth
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Publication number: 20120154961Abstract: Techniques and architectures corresponding to electrostatic discharge blocking circuits are described.Type: ApplicationFiled: December 21, 2010Publication date: June 21, 2012Applicant: Infineon Technologies AGInventors: Christian Russ, Wolfgang Soldner, Gernot Langguth, David Alvarez, Krzysztof Domanski, Klaus von Arnim
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Patent number: 8198651Abstract: A semiconductor device for protecting against an electro static discharge is disclosed. In one embodiment, the semiconductor device includes a first low doped region disposed in a substrate, a first heavily doped region disposed within the first low doped region, the first heavily doped region comprising a first conductivity type, and the first low doped region comprising a second conductivity type, the first and the second conductivity types being opposite, the first heavily doped region being coupled to a node to be protected. The semiconductor device further includes a second heavily doped region coupled to a first power supply potential node, the second heavily doped region being separated from the first heavily doped region by a portion of the first low doped region, and a second low doped region disposed adjacent the first low doped region, the second low doped region comprising the first conductivity type.Type: GrantFiled: October 13, 2008Date of Patent: June 12, 2012Assignee: Infineon Technologies AGInventors: Gernot Langguth, Wolfgang Soldner, Cornelius Christian Russ
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Publication number: 20120106010Abstract: A method and a system for ESD protection are provided. In one embodiment, the system comprises a circuit comprising at least one non-linear element, an application module configured to apply a set of current pulses to the circuit, a determination module configured to determine at least one frequency-dependent and amplitude-dependent transfer function of the circuit based on the set of applied current pulses, a modeling module configured to model at least one frequency-dependent and current-dependent impedance of the at least one non-linear element, and a simulation module to simulate a transmission to the circuit based on the model.Type: ApplicationFiled: October 27, 2010Publication date: May 3, 2012Inventors: Harald GOSSNER, David JOHNSSON, Wolfgang SOLDNER
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Publication number: 20120099229Abstract: An embodiment semiconductor device has a first device region disposed on a second device region within an ESD device region disposed within a semiconductor body. Also included is a third device region disposed on the second device region, a fourth device region adjacent to the second device region, a fifth device region disposed within the fourth device region, and a sixth device region adjacent to the fourth device region. The first and fourth regions have a first semiconductor type, and the second, third, fifth and sixth regions have a second conductivity type opposite the first conductivity type. An interface between the fourth device region and the sixth device region forms a diode junction. The first, second, fourth and fifth device regions form a silicon controlled rectifier.Type: ApplicationFiled: October 25, 2010Publication date: April 26, 2012Inventors: Krzysztof Domanski, Cornelius Christian Russ, David Alvarez, Wolfgang Soldner
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Patent number: 8133765Abstract: The invention relates to a high-frequency integrated circuit requiring ESD protection for a circuit node. One or more metallic layer is deposited within the integrated circuit and patterned to form a transmission line. The metallic layers are generally already present in the integrated circuit for signal routing. The transmission line is coupled between the circuit node and a terminal of an ESD protection device, with a transmission line return conductor coupled to a high-frequency ground. The transmission line is formed with an electrical length that transforms the impedance of the ESD protection device substantially into an open circuit at the circuit node at an operational frequency of the integrated circuit. The other terminal of the ESD protection device is coupled to the high-frequency ground.Type: GrantFiled: November 16, 2010Date of Patent: March 13, 2012Assignee: Infineon Technologies AGInventors: Uwe Hodel, Wolfgang Soldner
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Publication number: 20120002333Abstract: Embodiments of this disclosure relate to electrostatic discharge (ESD) protection techniques. For example, some embodiments include a variable resistor that selectively shunts power of an incoming ESD pulse from a first circuit node to a second circuit node and away from a semiconductor device. A control voltage provided to the variable resistor causes the transistor to change between a fully-off mode where only sub-threshold current, if any, flows; a fully-on mode wherein a maximum amount of current flows; and an analog mode wherein an intermediate and time-varying amount of current flows. In particular, the analog mode allows the ESD protection device to shunt power more precisely than previously achievable, such that the ESD protection device can protect semiconductor devices from ESD pulses.Type: ApplicationFiled: June 30, 2010Publication date: January 5, 2012Applicant: Infineon Technologies AGInventors: Wolfgang Soldner, Gernot Langguth, Christian Russ, Harald Gossner
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Patent number: 7973365Abstract: The invention relates to a high-frequency integrated circuit requiring ESD protection for a circuit node. One or more metallic layer is deposited within the integrated circuit and patterned to form a transmission line. The metallic layers are generally already present in the integrated circuit for signal routing. The transmission line is coupled between the circuit node and a terminal of an ESD protection device, with a transmission line return conductor coupled to a high-frequency ground. The transmission line is formed with an electrical length that transforms the impedance of the ESD protection device substantially into an open circuit at the circuit node at an operational frequency of the integrated circuit. The other terminal of the ESD protection device is coupled to the high-frequency ground.Type: GrantFiled: January 25, 2008Date of Patent: July 5, 2011Assignee: Infineon Technologies AGInventors: Uwe Hodel, Wolfgang Soldner
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Publication number: 20110063763Abstract: Implementations are presented herein that include an electrostatic discharge (ESD) protection circuit. The ESD protection circuit includes a first transistor and a second transistor. The first transistor has a first terminal that is coupled to a first supply line and a bulk that is coupled to a second supply line. The second transistor has a first terminal that is coupled to the second supply line, a bulk that is coupled to the first supply line and a second terminal that is coupled to a second terminal of the first transistor to define a protected node. The ESD protection circuit further includes a current limiting element that has a first terminal that is coupled to the protected node.Type: ApplicationFiled: September 16, 2009Publication date: March 17, 2011Inventors: David ALVAREZ, Krzysztof DOMANSKI, Gernot LANGGUTH, Christian RUSS, Wolfgang SOLDNER