Abstract: The invention relates to a program-controlled arrangement and a method for the identification of ESD and/or latch-up weak points in the design or in the concept of an integrated circuit, having a pre-processor, which processes first data about the description of the integrated circuit, second data about already ESD-characterized circuit parts of the integrated circuit, and third data which contain information about ESD test standards, having a simulator device connected downstream of the pre-processor, which has a simulator which, by using the fourth and fifth data generated by the pre-processor, performs an ESD simulation of the integrated circuit, which has a monitoring controller for controlling the ESD simulation sequence in the simulator, having an analysis device connected downstream of the simulator device, which performs an evaluation of the sixth data generated in the simulator device with regard to their physical validity and meaningfulness, and marks the simulation runs having physically relevant E

Abstract: An integrated semiconductor structure has a substrate, a semiconductor element located on the substrate, a pad metal, metal layers located between the pad metal and the substrate, and insulation layers that separate the metal layers from one another. The pad metal extends over at least—part of the semiconductor element. Below the surface of the pad metal, at least the top two metal layers include two or more adjacent interconnects.

Abstract: The invention relates to an internal combustion engine comprising a high-pressure accumulator injection system wherein the swept volume and the pressure are regulated by means of a volume flow control valve (VCV) and a pressure control valve (PCV). The inventive method consists in checking, during the overrun condition of the internal combustion engine, whether predetermined release conditions for carrying out the diagnosis are fulfilled, and in the event of a positive result, the control valve (VCV) is closed for a predetermined period of time (t1). During said period (t1), values relating to fuel pressure (FUP) are detected by means of the pressure sensor (21) and compared with a predetermined threshold value (FUP-SW), the control valve (VCV) being deemed faultless if said fuel pressure (FUP) values are sufficiently often below the threshold value (FUP_SW) during the cited period of time (t1).

Abstract: A circuit is described that protects an integrated circuit from electrostatic discharges or electrical over-stress. The circuit arrangement has first and second protective elements connected in series between a connection of the integrated circuit and a supply voltage. When electrostatic discharges or electrical over-stress occurs, current flows through the conductive path formed through the first and second protective elements. A current path that contains a circuit element limits current through the first protective element is connected in parallel with the first protective element. The first protective element has blocking behavior when no electrostatic discharges or electrical over-stress occurs, a limited current flows through the current path and the second protective element.

Abstract: To test the ESD resistance of a semiconductor component, for example of a NOS transistor, which can be used as a PSD protective element in a chip, a direct current characteristic of the semiconductor component is monitored and the ESD resistance of the respective semiconductor component is inferred depending on this. In particular, the direct current failure threshold of the semiconductor component at which an increased leakage current occurs in the non-conducting direction of the semiconductor component can be monitored in operation of the semiconductor component using an applied direct current and the ESD resistance of the semiconductor component inferred depending on a change in this direct current failure threshold.

Abstract: A measured value (MAP_MES) of the pressure in a suction pipe is the command variable of a control loop. The regulating variable is an estimated value (MAP_EST) of the pressure in the suction pipe, the estimated value being determined according to the manipulated variable of the control loop. The manipulated variable is calculated according to the difference between the estimated value (MAP_EST) and a measured value (MAP_MES) of the pressure in the suction pipe and according to the temporal change of the measured value (MAP_MES) of the pressure in the suction pipe. An estimated value (MAF_EST) of the mass flow in the intake passage (1) is calculated according to the manipulated variable.

Abstract: A semiconductor circuit containing a pad for electrical bonding of the semiconductor circuit and a metal arrangement disposed beneath the pad. The metal arrangement is in a metal layer of the semiconductor circuit located closest to the pad and is electrically insulated from the pad and from a strip conductor located beneath the metal arrangement. More than one metal layer can contain a metal arrangement. Each metal arrangement is a full-area plate that overlaps all edges of the pad or has a regular structure of small square plates. If adjacent metal arrangements are constructed from small plates, the plates in one metal arrangement overlap to cover gaps in the other metal arrangement.

Abstract: An integrated semiconductor structure has a substrate, a semiconductor element located on the substrate, a pad metal, metal layers located between the pad metal and the substrate, and insulation layers that separate the metal layers from one another. The pad metal extends over at least -part of the semiconductor element. Below the surface of the pad metal, at least the top two metal layers include two or more adjacent interconnects.

Abstract: A method for determining an ESD/latch-up strength of an integrated circuit includes producing an integrated circuit and a test structure using the same fabrication process. Electrical parameters at the test structure are measured and characteristic values associated with the integrated circuit are derived from the measured parameter values, wherein the characteristic values characterize an ESD or latch-up characteristic curve associated with the integrated circuit. The method further includes testing whether the characteristic values in each case lie within a predetermined range assigned to them, wherein the ranges are chosen such that a desired ESD/latch-up strength is present if the characteristic values in each case lie within their range.

Abstract: The present invention creates an operating method for a semiconductor component having a substrate; having a conductive polysilicon strip which is applied to the substrate; having a first and a second electrical contact which are connected to the conductive polysilicon strip such that this forms an electrical resistance in between them; with the semiconductor component being operated reversibly in a current/voltage range in which it has a first differential resistance (Rdiff1) up to a current limit value (It) corresponding to an upper voltage limit value (Vt) and, at current values greater than this, has a second differential resistance (Rdiff2), which is less than the first differential resistance (Rdiff1).

Abstract: A measured value (MAP_MES) of the pressure in a suction pipe is the command variable of a control loop. The regulating variable is an estimated value (MAP_EST) of the pressure in the suction pipe, said estimated value being determined according to the manipulated variable of the control loop. Said manipulated variable is calculated according to the difference between the estimated value (MAP_EST) and a measured value (MAP_MES) of the pressure in the suction pipe and according to the temporal change of the measured value (MAP_MES) of the pressure in the suction pipe. An estimated value (MAF_EST) of the mass flow in the intake passage (1) is calculated according to the manipulated variable.

Abstract: In a control method, the setting for a setting device (5), comprising a device (9) for reporting the setting, is regulated in a range between two end positions by using a measured parameter, given by the device (9) for reporting the setting, depending on the setting of the setting device and a characteristic curve, whereby, during the regulation a set value or an actual value for the setting is monitored. The characteristic curve is adapted when the set value or the actual value for the setting lies within a given separation from a given value for an adaptation setting.

Abstract: A method for determining an ESD/latch-up strength of an integrated circuit includes producing an integrated circuit and a test structure using the same fabrication process. Electrical parameters at the test structure are measured and characteristic values associated with the integrated circuit are derived from the measured parameter values, wherein the characteristic values characterize an ESD or latch-up characteristic curve associated with the integrated circuit. The method further includes testing whether the characteristic values in each case lie within a predetermined range assigned to them, wherein the ranges are chosen such that a desired ESD/latch-up strength is present if the characteristic values in each case lie within their range.

Abstract: In a control method, the setting for a setting device (5), comprising a device (9) for reporting the setting, is regulated in a range between two end positions by using a measured parameter, given by the device (9) for reporting the setting, depending on the setting of the setting device and a characteristic curve, whereby, during the regulation a set value or an actual value for the setting is monitored. The characteristic curve is adapted when the set value or the actual value for the setting lies within a given separation from a given value for an adaptation setting.

Abstract: A method for precisely controlling the charge pressure in an internal combustion engine with an exhaust-gas turbocharger is disclosed. According to said method, the output or torque of the turbine is determined based on the outputs or torques of the compressor and the loss on the shaft and the selected set point for the correcting variable for adjusting the charge pressure is determined according to said output or said torque of the turbine.

Abstract: A method for precisely controlling the charge pressure in an internal combustion engine with an exhaust-gas turbocharger is disclosed. According to said method, the output or torque of the turbine is determined based on the outputs or torques of the compressor and the loss on the shaft and the selected set point for the correcting variable for adjusting the charge pressure is determined according to said output or said torque of the turbine.

Abstract: The transistor has source and drain diffusion regions between which a gate electrode is disposed. In order to increase the sheet resistance of the source and/or drain diffusion regions, a plurality of strip-shaped insulating zones are provided, which penetrate through the corresponding diffusion region. The zones are oriented perpendicularly to the gate electrode and the end a given spacing distance from the gate electrode.

Abstract: The present invention creates an operating method for a semiconductor component having a substrate; having a conductive polysilicon strip which is applied to the substrate; having a first and a second electrical contact which are connected to the conductive polysilicon strip such that this forms an electrical resistance in between them; with the semiconductor component being operated reversibly in a current/voltage range in which it has a first differential resistance (Rdiff1) up to a current limit value (It) corresponding to an upper voltage limit value (Vt) and, at current values greater than this, has a second differential resistance (Rdiff2), which is less than the first differential resistance (Rdiff1).

Abstract: To test the ESD resistance of a semiconductor component (1), for example of a NOS transistor, which can be used as an PSD protective element in a chip (2), a direct current characteristic of the semiconductor component (1) is monitored and the ESD resistance of the respective semiconductor component (1) is inferred depending on this. In particular, the direct current failure threshold of the semiconductor component (1) at which an increased leakage current occurs in the non-conducting direction of the semiconductor component (1) can be monitored in operation of the semiconductor coponent (1) using an applied direct current (Io) and the ESD resistance of the semiconductor component (1) inferred depending on a change in this direct current failure threshold.

Abstract: The transistor has source and drain diffusion regions between which a gate electrode is disposed. In order to increase the sheet resistance of the source and/or drain diffusion regions, a plurality of strip-shaped insulating zones are provided, which penetrate through the corresponding diffusion region. The zones are oriented perpendicularly to the gate electrode and the end a given spacing distance from the gate electrode.