Abstract: An integrated circuit used in smart power technology, in particular, for use in automobile applications, which includes: high-voltage terminals for connection to a high voltage, a smart circuit device having low-voltage components, and an ESD protective circuit, connected between the high-voltage terminals, which has a MOSFET whose source and drain are connected to the high-voltage terminals, and whose gate is connected to its source via a resistor, the gate resistor being made of polycrystalline silicon. High ESD resistance with relatively low surface area usage and accordingly low costs may be achieved by using the polyresistor as the gate resistor. One protective diode, which blocks above the supply voltage, may be connected in the blocking direction between source and gate and between gate and drain of the MOSFET.

Abstract: An ESD protection device encompassing a vertical bipolar transistor that is connected as a diode and has an additional displaced base area. The assemblage has a space-saving configuration and a decreased difference between snapback voltage and breakdown voltage.

Abstract: An ESD protection device for an integrated circuit, which is integrated in a semiconductor substrate of the integrated circuit, has a heavily doped p-region provided with a first connection electrode, a heavily doped n-region provided with a second connection electrode, a lightly doped p-region bordering on the heavily doped p-region, and a lightly doped n-region bordering on the heavily doped n-region and the lightly doped p-region in such a way that the lightly doped regions are arranged at least between the heavily doped regions. The distance which exists between the lightly doped p-region and the heavily doped n-region and which is determined by the lightly doped n-region is dimensioned in such a way that the depletion zone in the lightly doped n-region, which becomes larger as the blocking voltage applied to the connection electrodes increases, reaches the heavily doped n-region before the breakthrough voltage between the lightly doped n-region and the lightly doped p-region has been reached.

Abstract: An ESD protective transistor comprises a heavily doped p-type base region which is arranged in a lightly doped p-well and which is provided with a first terminal. Furthermore, a heavily doped n-type emitter region is arranged in the lightly doped p-well. A heavily doped n-type collector region is separated from the lightly doped p-well through a lightly doped n-type region and is provided with a second terminal. The heavily doped n-type emitter region is not short-circuited with the heavily doped base region viy a common electrode and is of floating design. The doping types of the respective regions may be reversed.

Abstract: An ESD protection device is proposed, encompassing a vertical bipolar transistor that is connected as a diode and has an additional displaced base area. The assemblage according to the present invention has a space-saving configuration and a difference between snapback voltage and breakdown voltage that is decreased as compared to known assemblages.

Abstract: A circuit arrangement for the protection of integrated circuits against electrostatic discharges is described, the circuit arrangement having a first MOS protective transistor, a second MOS transistor being connected between the gate terminal and source terminal of the first MOS protective transistor, the second MOS transistor being connected with its drain terminal to the gate terminal of the first MOS transistor, being connected with its source terminal to the source terminal of the first MOS transistor, and being connected with its gate terminal to the drain terminal of the first MOS transistor. At least one diode is connected between the source terminal of the second MOS transistor and the source terminal of the MOS protective transistor.