Abstract: There is described a method, a bus protocol, a peripheral module, a processing unit, a hub and also to a system consisting of said components, for event signaling between at least one peripheral module and a processing unit by means of a system bus. In this case the data to be transmitted data is encoded into a larger symbol space, from which a standard idle symbol is used in telegram pauses for synchronizing a connection between transmitter and receiver. A message present at the peripheral modules is enabled to be signaled to the processing unit independently of the telegram traffic initiated by the processing unit.

Abstract: There is described a method, a bus protocol, a peripheral module, a processing unit, a hub and also to a system consisting of said components, for event signaling between at least one peripheral module and a processing unit by means of a system bus. In this case the data to be transmitted data is encoded into a larger symbol space, from which a standard idle symbol is used in telegram pauses for synchronizing a connection between transmitter and receiver. A message present at the peripheral modules is enabled to be signaled to the processing unit independently of the telegram traffic initiated by the processing unit.

Abstract: For optimization of the mode of operation of processor systems, there is proposed a bus connection which divides bus transactions substantially into transactions that must be executed in strictly logical sequence and that do not have to be executed in strictly logical sequence. Subsequently the transactions are again arrayed one after another in serial manner for further processing, with the feature that, in given cases, transactions that do not have to be executed in strictly logical sequence are moved ahead of transactions that must be executed in strictly logical sequence. The result is a gain in time and thus performance for the processor system.

Abstract: A cache memory device to increase the power of a processor system that operates with a cache memory device and with look-ahead read cycles for making available information bits needed by the processor system. The cache memory device automatically executes additional look-ahead read cycles and makes the additional information bits determined in this way available, in addition to the information bits obtained from read cycles in response to the processor system. The cache memory device may include an independent storage component or buffer for temporary storage of the additional bits.