Patents by Inventor Wolfram Hable
Wolfram Hable has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11955407Abstract: An electronic module includes a semiconductor package including a die carrier, a semiconductor transistor die disposed on the die carrier, an electrical conductor connected to the semiconductor die, and an encapsulant covering the die carrier, the semiconductor die, and the electrical conductor so that a portion of the electrical conductor extends to the outside of the encapsulant. The electronic module further includes an interposer layer on which the semiconductor package is disposed, and a heat sink through which a cooling medium can flow. The interposer layer is disposed on the heatsink.Type: GrantFiled: January 18, 2021Date of Patent: April 9, 2024Assignee: Infineon Technologies Austria AGInventors: Edward Fuergut, Davide Chiola, Martin Gruber, Wolfram Hable
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Patent number: 11862533Abstract: A package includes: at least one electronic chip; an encapsulant encapsulating at least part of the at least one electronic chip; a shielding layer on at least part of an external surface of the encapsulant; and a first heat removal body thermally coupled to the at least one electronic chip and configured for removing thermal energy from the at least one electronic chip to a cooling fluid. The encapsulant has a surface portion that extends in a surface region extending laterally directly adjacent to the first heat removal body. The surface portion of the encapsulant delimits part of a cooling cavity configured to guide the cooling fluid. The shielding layer covers the surface portion of the encapsulant. A corresponding electronic device, method of manufacturing the package, method of manufacturing the electronic device, vehicle, and method of using the electronic device are also described.Type: GrantFiled: December 21, 2021Date of Patent: January 2, 2024Assignee: Infineon Technologies AGInventors: Andreas Grassmann, Wolfram Hable, Juergen Hoegerl, Ivan Nikitin, Achim Strass
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Patent number: 11574889Abstract: A method of manufacturing a power module comprising two substrates is provided, wherein the method comprises disposing a compensation layer of a first thickness above a first substrate; disposing a second substrate above the compensation layer; and reducing the thickness of the compensation layer from the first thickness to a second thickness after the second substrate is disposed on the compensation layer.Type: GrantFiled: June 4, 2013Date of Patent: February 7, 2023Assignee: Infineon Technologies AGInventors: Ottmar Geitner, Wolfram Hable, Andreas Grassmann, Frank Winter, Christian Neugirg, Ivan Nikitin
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Publication number: 20220115293Abstract: A package includes: at least one electronic chip; an encapsulant encapsulating at least part of the at least one electronic chip; a shielding layer on at least part of an external surface of the encapsulant; and a first heat removal body thermally coupled to the at least one electronic chip and configured for removing thermal energy from the at least one electronic chip to a cooling fluid. The encapsulant has a surface portion that extends in a surface region extending laterally directly adjacent to the first heat removal body. The surface portion of the encapsulant delimits part of a cooling cavity configured to guide the cooling fluid. The shielding layer covers the surface portion of the encapsulant. A corresponding electronic device, method of manufacturing the package, method of manufacturing the electronic device, vehicle, and method of using the electronic device are also described.Type: ApplicationFiled: December 21, 2021Publication date: April 14, 2022Inventors: Andreas Grassmann, Wolfram Hable, Juergen Hoegerl, Ivan Nikitin, Achim Strass
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Patent number: 11244886Abstract: A package which comprises at least one electronic chip, an encapsulant encapsulating at least part of the at least one electronic chip, and a shielding layer on at least part of an external surface of the encapsulant configured for shielding an interior of the package with regard to cooling fluid for removing thermal energy from the at least one electronic chip.Type: GrantFiled: September 21, 2017Date of Patent: February 8, 2022Assignee: Infineon Technologies AGInventors: Andreas Grassmann, Wolfram Hable, Juergen Hoegerl, Ivan Nikitin, Achim Strass
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Publication number: 20210225734Abstract: An electronic module includes a semiconductor package including a die carrier, a semiconductor transistor die disposed on the die carrier, an electrical conductor connected to the semiconductor die, and an encapsulant covering the die carrier, the semiconductor die, and the electrical conductor so that a portion of the electrical conductor extends to the outside of the encapsulant. The electronic module further includes an interposer layer on which the semiconductor package is disposed, and a heat sink through which a cooling medium can flow. The interposer layer is disposed on the heatsink.Type: ApplicationFiled: January 18, 2021Publication date: July 22, 2021Inventors: Edward Fuergut, Davide Chiola, Martin Gruber, Wolfram Hable
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Patent number: 10615097Abstract: A chip carrier which comprises a thermally conductive and electrically insulating sheet, a first electrically conductive structure on a first main surface of the sheet, and a second electrically conductive structure on a second main surface of the sheet, wherein the first electrically conductive structure and the second electrically conductive structure extend beyond a lateral edge of the sheet.Type: GrantFiled: October 12, 2017Date of Patent: April 7, 2020Assignee: Infineon Technologies AGInventors: Andreas Grassmann, Wolfram Hable, Juergen Hoegerl, Angela Kessler, Ivan Nikitin, Achim Strass
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Patent number: 10461017Abstract: A power module which comprises a semiconductor chip, at least one cooling plate with at least one cooling channel thermally coupled to the semiconductor chip and being configured so that a coolant is guidable through the at least one cooling channel, and an encapsulant encapsulating at least part of the semiconductor chip and part of the at least one cooling channel, wherein at least part of a main surface of the cooling plate forms part of an external surface of the power module.Type: GrantFiled: August 1, 2017Date of Patent: October 29, 2019Assignee: Infineon Technologies AGInventors: Andreas Grassmann, Wolfram Hable, Juergen Hoegerl, Ivan Nikitin, Achim Strass
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Patent number: 10283432Abstract: A method of manufacturing a package, wherein the method comprises a forming a chip carrier by covering a thermally conductive and electrically insulating core on both opposing main surfaces thereof at least partially by a respective electrically conductive layer by brazing the respective electrically conductive layer on a respective one of the main surfaces; a mounting at least one electronic chip on the chip carrier; an electrically coupling an electrically conductive contact structure with the at least one electronic chip; and an encapsulating part of the electrically conductive contact structure, and at least part of the chip carrier and of the at least one electronic chip by a mold-type encapsulant.Type: GrantFiled: August 24, 2018Date of Patent: May 7, 2019Assignee: Infineon Technologies AGInventors: Mark Pavier, Wolfram Hable, Angela Kessler, Michael Sielaff, Anton Pugatschow, Charles Rimbert-Riviere, Marco Sobkowiak
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Publication number: 20190006260Abstract: A method of manufacturing a package, wherein the method comprises a forming a chip carrier by covering a thermally conductive and electrically insulating core on both opposing main surfaces thereof at least partially by a respective electrically conductive layer by brazing the respective electrically conductive layer on a respective one of the main surfaces; a mounting at least one electronic chip on the chip carrier; an electrically coupling an electrically conductive contact structure with the at least one electronic chip; and an encapsulating part of the electrically conductive contact structure, and at least part of the chip carrier and of the at least one electronic chip by a mold-type encapsulant.Type: ApplicationFiled: August 24, 2018Publication date: January 3, 2019Inventors: Mark PAVIER, Wolfram HABLE, Angela KESSLER, Michael SIELAFF, Anton PUGATSCHOW, Charles RIMBERT-RIVIERE, Marco SOBKOWIAK
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Patent number: 10128165Abstract: A package comprising at least one electronic chip, an encapsulant encapsulating at least part of the at least one electronic chip, a first electrically conductive contact structure extending partially within and partially outside of the encapsulant and being electrically coupled with at least one first terminal of at least one of the at least one electronic chip, and a second electrically conductive contact structure extending partially within and partially outside of the encapsulant and being electrically coupled with at least one second terminal of at least one of the at least one electronic chip, wherein at least a portion of the first electrically conductive contact structure and at least a portion of the second electrically conductive contact structure within the encapsulant are spaced in a direction between two opposing main surfaces of the package.Type: GrantFiled: October 28, 2017Date of Patent: November 13, 2018Assignee: Infineon Technologies AGInventors: Wolfram Hable, Andreas Grassmann, Juergen Hoegerl, Eduard Knauer, Michael Ledutke
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Patent number: 10079195Abstract: A semiconductor chip package is disclosed. The package includes a carrier, a plurality of semiconductor chips disposed on the carrier, a first encapsulation layer disposed above the semiconductor chips. A metallization layer is disposed above the first encapsulation layer, the metallization layer including a plurality of first metallic areas forming electrical connections between selected ones of the semiconductor chips. A second encapsulation layer is disposed above the solder resist layer. A plurality of external connectors are provided, each one of the external connectors being connected with one of the first metallic areas and extending outwardly through a surface of the second encapsulation layer.Type: GrantFiled: October 13, 2016Date of Patent: September 18, 2018Assignee: Infineon Technologies AGInventors: Wolfram Hable, Martin Gruber, Juergen Hoegerl
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Patent number: 10074590Abstract: A package which comprises a chip carrier, at least one electronic chip mounted on the chip carrier, an electrically conductive contact structure electrically coupled with the at least one electronic chip, and a mold-type encapsulant encapsulating part of the electrically conductive contact structure, and at least part of the chip carrier and of the at least one electronic chip, wherein the chip carrier comprises a thermally conductive and electrically insulating core covered on both opposing main surfaces thereof by a respective brazed electrically conductive layer.Type: GrantFiled: July 13, 2017Date of Patent: September 11, 2018Assignee: Infineon Technologies AGInventors: Mark Pavier, Wolfram Hable, Angela Kessler, Michael Sielaff, Anton Pugatschow, Charles Rimbert-Riviere, Marco Sobkowiak
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Patent number: 10037972Abstract: Various embodiments provide an electronic module comprising a interposer comprising a fluid channel formed in an electrically isolating material and an electrically conductive structured layer; at least one electronic chip attached to the electrically conductive layer and in thermal contact to the fluid channel; and a molded encapsulation formed at least partially around the at least one electronic chip, wherein the electrically conductive structured layer is directly formed on the electrically isolating material.Type: GrantFiled: April 25, 2016Date of Patent: July 31, 2018Assignee: Infineon Technologies AGInventors: Edward Fuergut, Martin Gruber, Wolfram Hable
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Publication number: 20180122720Abstract: A package comprising at least one electronic chip, an encapsulant encapsulating at least part of the at least one electronic chip, a first electrically conductive contact structure extending partially within and partially outside of the encapsulant and being electrically coupled with at least one first terminal of at least one of the at least one electronic chip, and a second electrically conductive contact structure extending partially within and partially outside of the encapsulant and being electrically coupled with at least one second terminal of at least one of the at least one electronic chip, wherein at least a portion of the first electrically conductive contact structure and at least a portion of the second electrically conductive contact structure within the encapsulant are spaced in a direction between two opposing main surfaces of the package.Type: ApplicationFiled: October 28, 2017Publication date: May 3, 2018Inventors: Wolfram HABLE, Andreas GRASSMANN, Juergen HOEGERL, Eduard KNAUER, Michael LEDUTKE
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Publication number: 20180102302Abstract: A chip carrier which comprises a thermally conductive and electrically insulating sheet, a first electrically conductive structure on a first main surface of the sheet, and a second electrically conductive structure on a second main surface of the sheet, wherein the first electrically conductive structure and the second electrically conductive structure extend beyond a lateral edge of the sheet.Type: ApplicationFiled: October 12, 2017Publication date: April 12, 2018Inventors: Andreas GRASSMANN, Wolfram HABLE, Juergen HOEGERL, Angela KESSLER, Ivan NIKITIN, Achim STRASS
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Publication number: 20180082925Abstract: A package which comprises at least one electronic chip, an encapsulant encapsulating at least part of the at least one electronic chip, and a shielding layer on at least part of an external surface of the encapsulant configured for shielding an interior of the package with regard to cooling fluid for removing thermal energy from the at least one electronic chip.Type: ApplicationFiled: September 21, 2017Publication date: March 22, 2018Inventors: Andreas GRASSMANN, Wolfram HABLE, Juergen HOEGERL, Ivan NIKITIN, Achim STRASS
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Publication number: 20180040537Abstract: A power module which comprises a semiconductor chip, at least one cooling plate with at least one cooling channel thermally coupled to the semiconductor chip and being configured so that a coolant is guidable through the at least one cooling channel, and an encapsulant encapsulating at least part of the semiconductor chip and part of the at least one cooling channel, wherein at least part of a main surface of the cooling plate forms part of an external surface of the power module.Type: ApplicationFiled: August 1, 2017Publication date: February 8, 2018Inventors: Andreas GRASSMANN, Wolfram Hable, Juergen Hoegerl, Ivan Nikitin, Achim Strass
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Publication number: 20170200666Abstract: A semiconductor chip package is disclosed. The package includes a carrier, a plurality of semiconductor chips disposed on the carrier, a first encapsulation layer disposed above the semiconductor chips. A metallization layer is disposed above the first encapsulation layer, the metallization layer including a plurality of first metallic areas forming electrical connections between selected ones of the semiconductor chips. A second encapsulation layer is disposed above the solder resist layer. A plurality of external connectors are provided, each one of the external connectors being connected with one of the first metallic areas and extending outwardly through a surface of the second encapsulation layer.Type: ApplicationFiled: October 13, 2016Publication date: July 13, 2017Applicant: Infineon Technologies AGInventors: Wolfram Hable, Martin Gruber, Juergen Hoegerl
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Publication number: 20170154835Abstract: An electronic module is provided, which comprises a first carrier; an electronic chip comprising at least one electronic component and arranged on the first carrier; a spacing element comprising a surface arranged on the electronic chip and being in thermal conductive connection with the at least one electronic component; a second carrier arranged on the spacing element; and a mold compound enclosing the electronic chip and the spacing element at least partially; wherein the spacing element comprises a material having a CTE value being matched with at least one other CTE.Type: ApplicationFiled: February 14, 2017Publication date: June 1, 2017Inventors: Christian Neugirg, Andreas Grassmann, Wolfram Hable, Ottmar Geitner, Frank Winter, Alexander Schwarz, Inpil Yoo