Patents by Inventor Wolfram Hable

Wolfram Hable has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10615097
    Abstract: A chip carrier which comprises a thermally conductive and electrically insulating sheet, a first electrically conductive structure on a first main surface of the sheet, and a second electrically conductive structure on a second main surface of the sheet, wherein the first electrically conductive structure and the second electrically conductive structure extend beyond a lateral edge of the sheet.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: April 7, 2020
    Assignee: Infineon Technologies AG
    Inventors: Andreas Grassmann, Wolfram Hable, Juergen Hoegerl, Angela Kessler, Ivan Nikitin, Achim Strass
  • Patent number: 10461017
    Abstract: A power module which comprises a semiconductor chip, at least one cooling plate with at least one cooling channel thermally coupled to the semiconductor chip and being configured so that a coolant is guidable through the at least one cooling channel, and an encapsulant encapsulating at least part of the semiconductor chip and part of the at least one cooling channel, wherein at least part of a main surface of the cooling plate forms part of an external surface of the power module.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: October 29, 2019
    Assignee: Infineon Technologies AG
    Inventors: Andreas Grassmann, Wolfram Hable, Juergen Hoegerl, Ivan Nikitin, Achim Strass
  • Patent number: 10283432
    Abstract: A method of manufacturing a package, wherein the method comprises a forming a chip carrier by covering a thermally conductive and electrically insulating core on both opposing main surfaces thereof at least partially by a respective electrically conductive layer by brazing the respective electrically conductive layer on a respective one of the main surfaces; a mounting at least one electronic chip on the chip carrier; an electrically coupling an electrically conductive contact structure with the at least one electronic chip; and an encapsulating part of the electrically conductive contact structure, and at least part of the chip carrier and of the at least one electronic chip by a mold-type encapsulant.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: May 7, 2019
    Assignee: Infineon Technologies AG
    Inventors: Mark Pavier, Wolfram Hable, Angela Kessler, Michael Sielaff, Anton Pugatschow, Charles Rimbert-Riviere, Marco Sobkowiak
  • Publication number: 20190006260
    Abstract: A method of manufacturing a package, wherein the method comprises a forming a chip carrier by covering a thermally conductive and electrically insulating core on both opposing main surfaces thereof at least partially by a respective electrically conductive layer by brazing the respective electrically conductive layer on a respective one of the main surfaces; a mounting at least one electronic chip on the chip carrier; an electrically coupling an electrically conductive contact structure with the at least one electronic chip; and an encapsulating part of the electrically conductive contact structure, and at least part of the chip carrier and of the at least one electronic chip by a mold-type encapsulant.
    Type: Application
    Filed: August 24, 2018
    Publication date: January 3, 2019
    Inventors: Mark PAVIER, Wolfram HABLE, Angela KESSLER, Michael SIELAFF, Anton PUGATSCHOW, Charles RIMBERT-RIVIERE, Marco SOBKOWIAK
  • Patent number: 10128165
    Abstract: A package comprising at least one electronic chip, an encapsulant encapsulating at least part of the at least one electronic chip, a first electrically conductive contact structure extending partially within and partially outside of the encapsulant and being electrically coupled with at least one first terminal of at least one of the at least one electronic chip, and a second electrically conductive contact structure extending partially within and partially outside of the encapsulant and being electrically coupled with at least one second terminal of at least one of the at least one electronic chip, wherein at least a portion of the first electrically conductive contact structure and at least a portion of the second electrically conductive contact structure within the encapsulant are spaced in a direction between two opposing main surfaces of the package.
    Type: Grant
    Filed: October 28, 2017
    Date of Patent: November 13, 2018
    Assignee: Infineon Technologies AG
    Inventors: Wolfram Hable, Andreas Grassmann, Juergen Hoegerl, Eduard Knauer, Michael Ledutke
  • Patent number: 10079195
    Abstract: A semiconductor chip package is disclosed. The package includes a carrier, a plurality of semiconductor chips disposed on the carrier, a first encapsulation layer disposed above the semiconductor chips. A metallization layer is disposed above the first encapsulation layer, the metallization layer including a plurality of first metallic areas forming electrical connections between selected ones of the semiconductor chips. A second encapsulation layer is disposed above the solder resist layer. A plurality of external connectors are provided, each one of the external connectors being connected with one of the first metallic areas and extending outwardly through a surface of the second encapsulation layer.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: September 18, 2018
    Assignee: Infineon Technologies AG
    Inventors: Wolfram Hable, Martin Gruber, Juergen Hoegerl
  • Patent number: 10074590
    Abstract: A package which comprises a chip carrier, at least one electronic chip mounted on the chip carrier, an electrically conductive contact structure electrically coupled with the at least one electronic chip, and a mold-type encapsulant encapsulating part of the electrically conductive contact structure, and at least part of the chip carrier and of the at least one electronic chip, wherein the chip carrier comprises a thermally conductive and electrically insulating core covered on both opposing main surfaces thereof by a respective brazed electrically conductive layer.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: September 11, 2018
    Assignee: Infineon Technologies AG
    Inventors: Mark Pavier, Wolfram Hable, Angela Kessler, Michael Sielaff, Anton Pugatschow, Charles Rimbert-Riviere, Marco Sobkowiak
  • Patent number: 10037972
    Abstract: Various embodiments provide an electronic module comprising a interposer comprising a fluid channel formed in an electrically isolating material and an electrically conductive structured layer; at least one electronic chip attached to the electrically conductive layer and in thermal contact to the fluid channel; and a molded encapsulation formed at least partially around the at least one electronic chip, wherein the electrically conductive structured layer is directly formed on the electrically isolating material.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: July 31, 2018
    Assignee: Infineon Technologies AG
    Inventors: Edward Fuergut, Martin Gruber, Wolfram Hable
  • Publication number: 20180122720
    Abstract: A package comprising at least one electronic chip, an encapsulant encapsulating at least part of the at least one electronic chip, a first electrically conductive contact structure extending partially within and partially outside of the encapsulant and being electrically coupled with at least one first terminal of at least one of the at least one electronic chip, and a second electrically conductive contact structure extending partially within and partially outside of the encapsulant and being electrically coupled with at least one second terminal of at least one of the at least one electronic chip, wherein at least a portion of the first electrically conductive contact structure and at least a portion of the second electrically conductive contact structure within the encapsulant are spaced in a direction between two opposing main surfaces of the package.
    Type: Application
    Filed: October 28, 2017
    Publication date: May 3, 2018
    Inventors: Wolfram HABLE, Andreas GRASSMANN, Juergen HOEGERL, Eduard KNAUER, Michael LEDUTKE
  • Publication number: 20180102302
    Abstract: A chip carrier which comprises a thermally conductive and electrically insulating sheet, a first electrically conductive structure on a first main surface of the sheet, and a second electrically conductive structure on a second main surface of the sheet, wherein the first electrically conductive structure and the second electrically conductive structure extend beyond a lateral edge of the sheet.
    Type: Application
    Filed: October 12, 2017
    Publication date: April 12, 2018
    Inventors: Andreas GRASSMANN, Wolfram HABLE, Juergen HOEGERL, Angela KESSLER, Ivan NIKITIN, Achim STRASS
  • Publication number: 20180082925
    Abstract: A package which comprises at least one electronic chip, an encapsulant encapsulating at least part of the at least one electronic chip, and a shielding layer on at least part of an external surface of the encapsulant configured for shielding an interior of the package with regard to cooling fluid for removing thermal energy from the at least one electronic chip.
    Type: Application
    Filed: September 21, 2017
    Publication date: March 22, 2018
    Inventors: Andreas GRASSMANN, Wolfram HABLE, Juergen HOEGERL, Ivan NIKITIN, Achim STRASS
  • Publication number: 20180040537
    Abstract: A power module which comprises a semiconductor chip, at least one cooling plate with at least one cooling channel thermally coupled to the semiconductor chip and being configured so that a coolant is guidable through the at least one cooling channel, and an encapsulant encapsulating at least part of the semiconductor chip and part of the at least one cooling channel, wherein at least part of a main surface of the cooling plate forms part of an external surface of the power module.
    Type: Application
    Filed: August 1, 2017
    Publication date: February 8, 2018
    Inventors: Andreas GRASSMANN, Wolfram Hable, Juergen Hoegerl, Ivan Nikitin, Achim Strass
  • Publication number: 20170200666
    Abstract: A semiconductor chip package is disclosed. The package includes a carrier, a plurality of semiconductor chips disposed on the carrier, a first encapsulation layer disposed above the semiconductor chips. A metallization layer is disposed above the first encapsulation layer, the metallization layer including a plurality of first metallic areas forming electrical connections between selected ones of the semiconductor chips. A second encapsulation layer is disposed above the solder resist layer. A plurality of external connectors are provided, each one of the external connectors being connected with one of the first metallic areas and extending outwardly through a surface of the second encapsulation layer.
    Type: Application
    Filed: October 13, 2016
    Publication date: July 13, 2017
    Applicant: Infineon Technologies AG
    Inventors: Wolfram Hable, Martin Gruber, Juergen Hoegerl
  • Publication number: 20170154835
    Abstract: An electronic module is provided, which comprises a first carrier; an electronic chip comprising at least one electronic component and arranged on the first carrier; a spacing element comprising a surface arranged on the electronic chip and being in thermal conductive connection with the at least one electronic component; a second carrier arranged on the spacing element; and a mold compound enclosing the electronic chip and the spacing element at least partially; wherein the spacing element comprises a material having a CTE value being matched with at least one other CTE.
    Type: Application
    Filed: February 14, 2017
    Publication date: June 1, 2017
    Inventors: Christian Neugirg, Andreas Grassmann, Wolfram Hable, Ottmar Geitner, Frank Winter, Alexander Schwarz, Inpil Yoo
  • Patent number: 9589922
    Abstract: An electronic module is provided, which comprises a first carrier; an electronic chip comprising at least one electronic component and arranged on the first carrier; a spacing element comprising a surface arranged on the electronic chip and being in thermal conductive connection with the at least one electronic component; a second carrier arranged on the spacing element; and a mold compound enclosing the electronic chip and the spacing element at least partially; wherein the spacing element comprises a material having a CTE value being matched with at least one other CTE.
    Type: Grant
    Filed: March 16, 2014
    Date of Patent: March 7, 2017
    Assignee: Infineon Technologies AG
    Inventors: Christian Neugirg, Andreas Grassmann, Wolfram Hable, Ottmar Geitner, Frank Winter, Alexander Schwarz, Inpil Yoo
  • Patent number: 9585241
    Abstract: In various embodiments, a substrate is provided. The substrate may include: a ceramic carrier having a first side and a second side opposite the first side; a first metal layer disposed over the first side of the ceramic carrier; a second metal layer disposed over the second side of the ceramic carrier; and a cooling structure formed into or over the second metal layer.
    Type: Grant
    Filed: September 24, 2013
    Date of Patent: February 28, 2017
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Wolfram Hable, Andreas Grassmann, Frank Winter, Ottmar Geitner, Alexander Schwarz, Alexander Herbrandt
  • Publication number: 20160322333
    Abstract: Various embodiments provide an electronic module comprising a interposer comprising a fluid channel formed in an electrically isolating material and an electrically conductive structured layer; at least one electronic chip attached to the electrically conductive layer and in thermal contact to the fluid channel; and a molded encapsulation formed at least partially around the at least one electronic chip, wherein the electrically conductive structured layer is directly formed on the electrically isolating material.
    Type: Application
    Filed: April 25, 2016
    Publication date: November 3, 2016
    Inventors: Edward FUERGUT, Martin GRUBER, Wolfram HABLE
  • Patent number: 9397018
    Abstract: A chip arrangement is provided, the chip arrangement, including a carrier; at least one chip electrically connected to a carrier top side; an encapsulation material at least partially surrounding the at least one chip and the carrier top side, wherein the encapsulation material is formed on one or more lateral sides of the carrier; and a ceramic material disposed on a carrier bottom side, and on at least one side of the encapsulation material.
    Type: Grant
    Filed: January 16, 2013
    Date of Patent: July 19, 2016
    Assignee: Infineon Technologies AG
    Inventors: Ralf Otremba, Josef Hoeglauer, Juergen Schredl, Xaver Schloegel, Wolfram Hable, Manfred Mengel, Joachim Mahler, Khalil Hosseini
  • Patent number: 9362193
    Abstract: A chip arrangement is provided, the chip arrangement, including a carrier; at least one chip electrically connected to a carrier top side; an encapsulation material at least partially surrounding the at least one chip and the carrier top side, wherein the encapsulation material is formed on one or more lateral sides of the carrier; and a ceramic material disposed on a carrier bottom side, and on at least one side of the encapsulation material.
    Type: Grant
    Filed: January 16, 2013
    Date of Patent: June 7, 2016
    Assignee: Infineon Technologies AG
    Inventors: Ralf Otremba, Josef Hoeglauer, Juergen Schredl, Xaver Schloegel, Wolfram Hable, Manfred Mengel, Joachim Mahler, Khalil Hosseini
  • Patent number: 9275926
    Abstract: According to an exemplary embodiment, a power module is provided which comprises a semiconductor chip, a bonding substrate comprising an electrically conductive sheet and an electric insulator sheet which is directly attached to the electrically conductive sheet and which is thermally coupled to the semiconductor chip, and an array of cooling structures directly attached to the electrically conductive sheet and configured for removing heat from the semiconductor chip when interacting with cooling fluid.
    Type: Grant
    Filed: May 3, 2013
    Date of Patent: March 1, 2016
    Assignee: Infineon Technologies AG
    Inventors: Wolfram Hable, Andreas Grassmann, Frank Winter, Ottmar Geitner, Alexander Schwarz, Alexander Herbrandt, Lothar Koenig, Andre Uhlemann