Abstract: A backing plate for a sputter target includes a target receiving part for receiving a target to be sputtered, and a structure for exposing the target receiving part through the backing plate.

Abstract: A backing plate for a sputter target includes a target receiving part for receiving a target to be sputtered, and a structure for exposing the target receiving part through the backing plate.

Abstract: A semiconductor memory cell is formed in a substrate and includes a trench capacitor and a selection transistor. The trench capacitor includes a capacitor dielectric and a conductive trench filling. Disposed on the conductive trench filling is a diffusion barrier on which an epitaxial layer is formed. The selection transistor is disposed as a planar transistor above the trench capacitor. A drain doping region of the selection transistor is disposed in the epitaxial layer.

Abstract: A trench capacitor for use in a semiconductor memory cell is formed in a substrate and includes a trench having an upper region and a lower region. An insulation collar is formed in the upper region of the trench. The lower region of the trench extends through a buried well. A dielectric layer, which is formed from tungsten oxide, serves as a capacitor dielectric. A conductive trench filling, which is filled into the trench, is formed from silicon or a tungsten-containing material such as tungsten, tungsten silicide or tungsten nitride.

Abstract: A method for fabricating an integrated circuit includes providing an intermediate layer on first and second metallization regions on a substrate. The intermediate layer above the first metallization region is then etched away, thereby allowing an oxide film to form above the first metallization region. Chemical vapor deposition is then performed using a gas having constituents that include the metal used for the metallization regions and a halogen. This partially converts the oxide layer into a conductive compound in electrical communication with the first metallization region.

Abstract: In a method for forming a trench capacitor a first layer of silicon oxide is deposited in a storage trench and a layer of silicon is deposited over the first layer by a chemical vapor deposition process. A layer of an oxidizable metal is deposited over the layer of silicon. The layer of silicon and the layer of the oxidizable metal are subsequently oxidized to form a layer of silicon oxide and metal oxide.

Abstract: A memory having a memory cell formed in a substrate and including a trench capacitor and a transistor and a method for producing the memory includes connecting the trench capacitor to the transistor with a self-aligned connection. The transistor at least partly covers the trench capacitor. The trench capacitor is filled with a conductive trench filling and an insulating covering layer is situated on the conductive trench filling. An epitaxial layer is situated above the insulating covering layer. The transistor is formed in the epitaxial layer. The self-aligned connection is formed in a contact trench and includes an insulation collar in which a conductive material is introduced. A conductive cap is formed on the conductive material.

Abstract: A semiconductor memory cell is formed in a substrate and includes a trench capacitor and a selection transistor. The trench capacitor includes a capacitor dielectric and a conductive trench filling. Disposed on the conductive trench filling is a diffusion barrier on which an epitaxial layer is formed. The selection transistor is disposed as a planar transistor above the trench capacitor. A drain doping region of the selection transistor is disposed in the epitaxial layer.

Abstract: In a method for forming a trench capacitor a first layer of silicon oxide is deposited in a storage trench and a layer of silicon is deposited over the first layer by a chemical vapor deposition process. A layer of an oxidizable metal is deposited over the layer of silicon. The layer of silicon and the layer of the oxidizable metal are subsequently oxidized to form a layer of silicon oxide and metal oxide.

Abstract: A memory having a memory cell formed in a substrate and including a trench capacitor and a transistor and a method for producing the memory includes connecting the trench capacitor to the transistor with a self-aligned connection. The transistor at least partly covers the trench capacitor. The trench capacitor is filled with a conductive trench filling and an insulating covering layer is situated on the conductive trench filling. An epitaxial layer is situated above the insulating covering layer. The transistor is formed in the epitaxial layer. The self-aligned connection is formed in a contact trench and includes an insulation collar in which a conductive material is introduced. A conductive cap is formed on the conductive material.

Abstract: A method of fabricating an epitaxial layer includes providing a substrate having a substrate surface with an at least partly uncovered monocrytalline region, and at least one electrically insulating region adjoining the monocrystalline region and being at least partly surrounded by the monocrystalline region. An epitaxial layer is grown on the monocrystalline region. The electrically insulating region is at least partly overgrown laterally with the epitaxial layer, thereby forming an epitaxial closing joint above the electrically insulating region due to the overgrowth. The epitaxial layer is at least partly removed above the electrically insulating region, thereby the epitaxial closing joint is at least partly removed.

Abstract: In a method for forming a trench capacitor a first layer of silicon oxide is deposited in a storage trench and a layer of silicon is deposited over the first layer by a chemical vapor deposition process. A layer of an oxidizable metal is deposited over the layer of silicon. The layer of silicon and the layer of the oxidizable metal are subsequently oxidized to form a layer of silicon oxide and metal oxide.

Abstract: In chemical gaseous phase deposition (CVD=Chemical Vapor Deposition), there is frequently the problem of there still being an aggressive gas in the reaction chamber from the preceding layer production process. The aggressive gas can be a remainder of a process gas used for layer production or it can be a remainder gas produced by the reaction of the process gasses. The aggressive gas can cause undesirable reactions on the surface of the semiconductor product, which damage the semiconductor product. A process for layer production on a surface includes supplying at least one protective gas to the surface before and/or during the heating of the surface to the reaction temperature.