Abstract: One or more embodiments are related to a semiconductor device, comprising: a high-K dielectric material; and a nitrogen-doped silicon material disposed over said high-k dielectric material.

Abstract: In an embodiment of the invention, a memory cell arrangement includes a substrate and at least one memory cell including a charge storing memory cell structure and a select structure. The memory cell arrangement further includes a first doping well, a second doping well and a third doping well arranged within the substrate, wherein the charge storing memory cell structure is arranged in or above the first doping well, the first doping well is arranged within the second doping well, and the second doping well is arranged within the third doping well. The memory cell arrangement further includes a control circuit coupled with the memory cell and configured to control the memory cell such that the charge storing memory cell structure is programmed or erased by charging or discharging the charge storing memory cell structure via at least the first doping well.

Abstract: The invention provides a semiconductor product (25) and a method for forming the semiconductor product (25), the semiconductor product (25) comprising a transistor (1) having first (11) and second source/drain regions (12) being arranged at bottom surfaces (B) of recesses (R) in a substrate (2). Due to the depth (d) of the recesses (R) a vertical offset (29) between the source/drain regions (11, 12) and a gate dielectric (4) is achieved. The vertical offset (29) allows reducing a lateral offset (28) between the source/drain regions (11, 12) and the gate dielectric (4). Thereby, the substrate surface area required for a transistor is reduced. In particular in high voltage areas of semiconductor products like memory devices, substrate area is used more efficiently.

Abstract: A programmable read-only memory cell and method of operating the programmable read-only memory cell. In one embodiment, the programmable read-only memory cell comprises a floating gate arranged in a trench, an epitaxial channel layer formed on the floating gate, the channel layer connecting a source electrode to a drain electrode, and a selection gate arranged above the channel line.

Abstract: The disclosed embodiments relate to a method for the production of a layer arrangement, a layer arrangement and a memory arrangement. According to one aspect at least one respectively laterally defined first layer sequence is embodied on a first surface area of a substrate and at least one respectively laterally defined second layer sequence is embodied on a second surface area of the substrate in order to produce a layer arrangement. A first side wall having a first thickness is respectively produced from a first electrically insulating material on at least one partial area of the side walls of the first and second layer sequences. A second side wall layer having a second thickness is respectively produced from a second electrically insulating material on at least one partial area of the first side wall layers and the second side wall layers are removed from the first layer sequences.

Abstract: A method for fabricating embedded nonvolatile semiconductor memory cells is described. The method includes forming a first insulating layer on a substrate having a high-voltage region, a memory region and a logic region. The first insulating layer is removed in the memory region, and a second insulating layer is formed. A charge-storing layer is formed and patterned along with a third insulating layer. The first to third insulating layers and also the charge-storing layer are removed in the logic region. A fourth insulating layer is formed and a conductive control layer is formed and patterned.

Abstract: A programmable read-only memory cell and method of operating the programmable read-only memory cell. In one embodiment, the programmable read-only memory cell comprises a floating gate arranged in a trench, an epitaxial channel layer formed on the floating gate, the channel layer connecting a source electrode to a drain electrode, and a selection gate arranged above the channel line.

Abstract: A method for fabricating embedded nonvolatile semiconductor memory cells is described. The method includes forming a first insulating layer on a substrate having a high-voltage region, a memory region and a logic region. The first insulating layer is removed in the memory region, and a second insulating layer is formed. A charge-storing layer is formed and patterned along with a third insulating layer. The first to third insulating layers and also the charge-storing layer are removed in the logic region. A fourth insulating layer is formed and a conductive control layer is formed and patterned.