Abstract: In a communication network for transferring signals, e.g. according to the SONET or SDH standards, interconnecting node devices are provided consisting of parallel processing modules (9-T, 9-R). A plurality of processing modules with first and second interfaces rearrange/insert/extract tributary signals and configurable multiplexing/de-multiplexing components enable each processing module to access any portion of an arbitrarily preselected tributary signal. In a SONET/SDH system, signals between SONET/SDH frames are rearranged on incoming (20) and outgoing (26) main lines=Digital Cross-Connect, or tributary signals are transferred between frames and local lines (16-i-T, 16-i-R)=Add/Drop Function.

Abstract: A modular approach to the mapping of data in and from a standard SDH/SONET signal is described. A module has interfaces (T0-T8) which allows to connect to it to other of its kind and thereby achieving higher data rates, i.e. access to standard signals of higher levels. By choosing among different interconnection schemes, arrangements comprising a plurality of modules are also able to support concatenated data traffic.

Abstract: An apparatus for rapidly determining a control parameter t=t.sub.0 at which the sum S of n functions F.sub.i (i=1, . . . n) reaches a minimum, a maximum, or a given value, wherein each function F.sub.i (t) changes its first derivative only at given discrete values t.sub.ij of the control parameter t is described. The apparatus has a random access memory (RAM) addressed by the values t.sub.ij, a circuit for summing the second derivatives of the functions, a circuit to perform a double integration to evaluate S, and a comparator to determine the optimum control value; also disclosed is a new gate array (GA) which rapidly reproduces the addresses used to address the RAM while skipping all others. This gate array is advantageously used as a part of the apparatus for determining a control parameter. Further, the use of the devices in a communication network is described.

Abstract: An apparatus for rapidly determining a control parameter t=t.sub.0 at which the sum S of n functions F.sub.i (i=1, . . . n) reaches a minimum, a maximum, or a given value, wherein each function F.sub.i (t) changes its first derivative only at given discrete values t.sub.ij of the control parameter t is described. The apparatus has a random access memory (RAM) addressed by the values t.sub.ij, a circuit for summing the second derivatives of the functions, a circuit to perform a double integration to evaluate S, and a comparator to determine the optimum control value; also disclosed is a new gate array (GA) which rapidly reproduces the addresses used to address the RAM while skipping all others. This gate array is advantageously used as a part of the apparatus for determining a control parameter. Further, the use of the devices in a communication network is described.

Abstract: In a communication system comprising several nodes and a scheduler interconnected by a serial transmission medium, data are transmitted in time slots. The scheduler marks time slots either as reserved if nodes have previously made a request and received a confirmation, or it marks time slots as gratis for free use by any node. Slots are also marked gratis if the have reached their destination or removal node. To achieve fairness between nodes in the reservation process, they count gratis slots they used. When making a request for reserving a number NR of slots, a node must also transmit the number NG of gratis slots used. The scheduler then determines, according to a given rule, the number NC of slots to be granted for each node. A special signalling technique is also disclosed for effective transmission of the numbers in the reservation and confirmation process.

Abstract: In a communication system comprising several nodes and a scheduler interconnected by a serial transmission medium, signalling information is transmitted by inserting it whenever required in the data stream in the form of basic data units (ADU). The scheduler inserts a request start and an end flag, and any node requiring allocation of a given type of service insert its request unit between the flags. Thus, the scheduler receives accumulated node-individual request information. The scheduler then sends a response comprising individual response units between two delimiting flags. Each node having made a request removes the respective individual response unit so that only the flags return to the scheduler. Special pipelined circuitry allows insertion and removel of the basic data units constituting the signalling information at very high speed without impeding the speed and timing of the passing data stream.