Patents by Inventor Wolfram M. Sauer
Wolfram M. Sauer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8943301Abstract: Methods for storing branch information in an address table of a processor are disclosed. A processor of the disclosed embodiments may generally include an instruction fetch unit connected to an instruction cache, a branch execution unit, and an address table being connected to the instruction fetch unit and the branch execution unit. The address table may generally be adapted to store a plurality of entries with each entry of the address table being adapted to store a base address and a base instruction tag. In a further embodiment, the branch execution unit may be adapted to determine the address of a branch instruction having an instruction tag based on the base address and the base instruction tag of an entry of the address table associated with the instruction tag. In some embodiments, the address table may further be adapted to store branch information.Type: GrantFiled: May 5, 2011Date of Patent: January 27, 2015Assignee: International Business Machines CorporationInventors: Brian R. Konigsburg, David Stephen Levitan, Wolfram M. Sauer, Samuel Jonathan Thomas
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Publication number: 20110213951Abstract: Methods for storing branch information in an address table of a processor are disclosed. A processor of the disclosed embodiments may generally include an instruction fetch unit connected to an instruction cache, a branch execution unit, and an address table being connected to the instruction fetch unit and the branch execution unit. The address table may generally be adapted to store a plurality of entries with each entry of the address table being adapted to store a base address and a base instruction tag. In a further embodiment, the branch execution unit may be adapted to determine the address of a branch instruction having an instruction tag based on the base address and the base instruction tag of an entry of the address table associated with the instruction tag. In some embodiments, the address table may further be adapted to store branch information.Type: ApplicationFiled: May 5, 2011Publication date: September 1, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brian R. Konigsburg, David Stephen Levitan, Wolfram M. Sauer, Samuel Jonathan Thomas
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Patent number: 7984280Abstract: Methods for storing branch information in an address table of a processor are disclosed. A processor of the disclosed embodiments may generally include an instruction fetch unit connected to an instruction cache, a branch execution unit, and an address table being connected to the instruction fetch unit and the branch execution unit. The address table may generally be adapted to store a plurality of entries with each entry of the address table being adapted to store a base address and a base instruction tag. In a further embodiment, the branch execution unit may be adapted to determine the address of a branch instruction having an instruction tag based on the base address and the base instruction tag of an entry of the address table associated with the instruction tag. In some embodiments, the address table may further be adapted to store branch information.Type: GrantFiled: July 11, 2008Date of Patent: July 19, 2011Assignee: International Business Machines CorporationInventors: Brian R. Konigsburg, David Stephen Levitan, Wolfram M. Sauer, Samuel Jonathan Thomas
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Patent number: 7890738Abstract: A method and logical apparatus for managing processing system resource use for speculative execution reduces the power and performance burden associated with inefficient speculative execution of program instructions. A measure of the efficiency of speculative execution is used to reduce resources allocated to a thread while the speculation efficiency is low. The resource control applied may be the number of instruction fetches allocated to the thread or the number of execution time slices. Alternatively, or in combination, the size of a prefetch instruction storage allocated to the thread may be limited. The control condition may be comparison of the number of correct or incorrect speculations to a threshold, comparison of the number of correct to incorrect speculations, or a more complex evaluator such as the size of a ratio of incorrect to total speculations.Type: GrantFiled: January 20, 2005Date of Patent: February 15, 2011Assignee: International Business Machines CorporationInventors: Lee Evan Eisen, David Stephen Levitan, Francis Patrick O'Connell, Wolfram M. Sauer
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Publication number: 20100262813Abstract: Mechanisms, in a processor, are provided for detecting and handling short forward branch conversion candidates. The mechanisms identify a conditional branch in the computer code and determine if the short forward conditional branch is to be converted to a non-branching conditional sequence of instructions. Moreover, the mechanisms convert the conditional branch to a non-branching conditional sequence of instructions comprising a resolve instruction and one or more conditional instructions dependent on the resolve instruction. In addition, the mechanisms execute the non-branching conditional sequence of instructions in place of the conditional branch in the computer code and generate an output of the computer code based on the execution of the non-branching conditional sequence of instructions.Type: ApplicationFiled: April 14, 2009Publication date: October 14, 2010Applicant: International Business Machines CorporationInventors: Mary D. Brown, Richard W. Doing, Kevin N. Magill, Brian R. Mestan, Wolfram M. Sauer, Balaram Sinharoy, Jeffrey R. Summers, Albert J. Van Norstrand, JR.
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Publication number: 20080276080Abstract: Methods for storing branch information in an address table of a processor are disclosed. A processor of the disclosed embodiments may generally include an instruction fetch unit connected to an instruction cache, a branch execution unit, and an address table being connected to the instruction fetch unit and the branch execution unit. The address table may generally be adapted to store a plurality of entries with each entry of the address table being adapted to store a base address and a base instruction tag. In a further embodiment, the branch execution unit may be adapted to determine the address of a branch instruction having an instruction tag based on the base address and the base instruction tag of an entry of the address table associated with the instruction tag. In some embodiments, the address table may further be adapted to store branch information.Type: ApplicationFiled: July 11, 2008Publication date: November 6, 2008Applicant: International Business Machines CorporationInventors: Brian R. Konigsburg, David Stephen Levitan, Wolfram M. Sauer, Samuel Jonathan Thomas
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Patent number: 7426631Abstract: Methods and systems for storing branch information in an address table of a processor are disclosed. A processor of the disclosed embodiments may generally include an instruction fetch unit connected to an instruction cache, a branch execution unit, and an address table being connected to the instruction fetch unit and the branch execution unit. The address table may generally be adapted to store a plurality of entries with each entry of the address table being adapted to store a base address and a base instruction tag. In a further embodiment, the branch execution unit may be adapted to determine the address of a branch instruction having an instruction tag based on the base address and the base instruction tag of an entry of the address table associated with the instruction tag. In some embodiments, the address table may further be adapted to store branch information.Type: GrantFiled: February 2, 2005Date of Patent: September 16, 2008Assignee: International Business Machines CorporationInventors: Brian R. Konigsburg, David Stephen Levitan, Wolfram M. Sauer, Samuel Jonathan Thomas
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Patent number: 6938148Abstract: A Storage Reference Buffer (SRB) designed as an autonomous unit for all Store operations that transfer data from the execution unit of a processor to the memory hierarchy and Load operations that transfer data from the memory hierarchy to the execution unit of the processor. The SRB partitions up the Load and Store operations into several smaller operations in order to perform them in parallel with other Load and Store requests. System elements are included to determine unambiguously which of these Load and Store operations may be performed without waiting for prior operations to be completed. The SRB also includes system elements to detect whether requests may be satisfied by existing entries in the SRB without having to access the cache. The SRB is operated as a content addressable memory. Load request are simultaneously launched to cache and to the SRB with the Cache request being canceled if the Load request may be satisfied by an SRB entry.Type: GrantFiled: December 15, 2000Date of Patent: August 30, 2005Assignee: International Business Machines CorporationInventors: Charles Roberts Moore, Ravi Nair, Wolfram M. Sauer
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Publication number: 20040073775Abstract: A Storage Reference Buffer (SRB) designed as an autonomous unit for all Store operations that transfer data from the execution unit of a processor to the memory hierarchy and Load operations that transfer of data from the memory hierarchy to the execution unit of the processor. The SRB partitions up the Load and Store operations into several smaller operations in order to perform them in parallel with other Load and Store requests. System elements are included to determine unambiguously which of these Load and Store operations may be performed without waiting for prior operations to be completed. The SRB also includes system elements to detect whether requests may be satisfied by existing entries in the SRB without having to access the cache. The SRB is operated as a content addressable memory. Load request are simultaneously launched to cache and to the SRB with the Cache request being canceled if the Load request may be satisfied by an SRB entry.Type: ApplicationFiled: December 15, 2000Publication date: April 15, 2004Applicant: International Business Machines CorporationInventors: Charles Roberts Moore, Ravi Nair, Wolfram M. Sauer