Abstract: A multiplier in which m-1 place multiplicands can be operated with the multiplier with n-1 place multiplier factors that are represented as binary numbers. In order to achieve a regularly constructed and easily testable arrangement of the multiplier on a chip, one cell (SL) is provided per product place. This cell is composed of AND circuits (UD) for the formation of the partial products allocated to this product place and of adder circuits (AD) for summing up the partial products for this product place. The number of AND circuits and of adder circuits is identical for all cells (SL). Those AND circuits that are not required per product place for generating partial products are applied to 0. Since the individual cells are identically constructed, they can be easily produced from basic circuits and can be easily arranged side-by-side. When a multiplier for multiplicands and multiplier factors having greater width is then to be produced, a further attachment of such cells is merely required.