Patents by Inventor Won-Bong Jung
Won-Bong Jung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10804194Abstract: A semiconductor device comprises a peripheral circuit region provided on a first substrate and including circuit devices and a contact plug extending on the first substrate in a vertical direction; a memory cell region provided on a second substrate disposed above the first substrate and including memory cells; and a through insulating region penetrating through the second substrate on the contact plug and covering an upper surface of the contact plug.Type: GrantFiled: February 22, 2018Date of Patent: October 13, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Gang Zhang, Kwang Soo Kim, Won Bong Jung
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Publication number: 20190051599Abstract: A semiconductor device comprises a peripheral circuit region provided on a first substrate and including circuit devices and a contact plug extending on the first substrate in a vertical direction; a memory cell region provided on a second substrate disposed above the first substrate and including memory cells; and a through insulating region penetrating through the second substrate on the contact plug and covering an upper surface of the contact plug.Type: ApplicationFiled: February 22, 2018Publication date: February 14, 2019Inventors: Gang Zhang, Kwang Soo Kim, Won Bong Jung
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Patent number: 10079203Abstract: A vertical memory device includes a substrate, a plurality of channels on the substrate and extending in a vertical direction with respect to a top surface of the substrate, a plurality of non-metal gate patterns surrounding the channels and being stacked on top of each other and spaced apart from each other along the vertical direction, and a plurality of metal gate patterns stacked on top of each other. The metal gate patterns are spaced apart from each other along the vertical direction. Each of the metal gate patterns surrounds a corresponding one of the non-metal gate patterns.Type: GrantFiled: September 21, 2016Date of Patent: September 18, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Hoon Son, Cha-Dong Yeo, Han-Mei Choi, Kyung-Hyun Kim, Phil-Ouk Nam, Kwang-Chul Park, Yeon-Sil Sohn, Jin-I Lee, Won-Bong Jung
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Patent number: 9997534Abstract: A vertical memory device includes a substrate, a channel on the substrate, extending in a vertical direction with respect to a top surface of the substrate, and including a protrusion at a lower portion of the channel, the protrusion extending in a parallel direction with respect to the top surface of the substrate, a semiconductor pattern connecting the protrusion and the substrate, and gate lines stacked and spaced apart from each other in the vertical direction, the gate lines on the protrusion and the semiconductor pattern and surrounding the channel.Type: GrantFiled: May 16, 2016Date of Patent: June 12, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Hoon Son, Kyung-Hyun Kim, Byeong-Ju Kim, Phil-Ouk Nam, Kwang Chul Park, Yeon-Sil Sohn, Jin-I Lee, Jong-Heun Lim, Won-Bong Jung, Kohji Kanamori
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Patent number: 9905568Abstract: A nonvolatile memory device includes a conductive line disposed on a substrate and vertically extended from the substrate, a first channel layer disposed on the substrate and vertically extended from the substrate, wherein the first channel layer is spaced apart from the conductive line, a second channel layer vertically extended from the substrate, wherein the second channel layer is disposed between the first channel layer and the conductive line, a first gate electrode disposed between the conductive line and the second channel layer, wherein the first gate electrode includes a first portion having a first thickness and a second portion having a second thickness that is different from the first thickness, and a second gate electrode disposed between the first channel layer and the second channel layer, wherein the second gate electrode has the second thickness.Type: GrantFiled: August 30, 2016Date of Patent: February 27, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yong-Hoon Son, Jong-Won Kim, Chang-Seok Kang, Young-Woo Park, Jae-Duk Lee, Kyung-Hyun Kim, Byeong-Ju Kim, Phil-Ouk Nam, Kwang-Chul Park, Yeon-Sil Sohn, Jin-I Lee, Won-Bong Jung
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Patent number: 9893077Abstract: A memory device, including a first memory region including a first substrate, a plurality of first semiconductor devices on the first substrate, and a first interlayer insulating layer covering the plurality of first semiconductor devices; and a second memory region including a second substrate on the first interlayer insulating layer and a plurality of second semiconductor devices on the second substrate, the second substrate including a first region in a plurality of grooves in the first interlayer insulating layer and a second region including grains extending from the first region, the second region being on an upper surface of the first interlayer insulating layer.Type: GrantFiled: February 22, 2016Date of Patent: February 13, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Phil Ouk Nam, Yong Hoon Son, Kyung Hyun Kim, Byeong Ju Kim, Kwang Chul Park, Yeon Sil Sohn, Jin I Lee, Jong Heun Lim, Won Bong Jung
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Patent number: 9806204Abstract: A method of manufacturing a semiconductor device, the method including forming a tunnel insulating layer on an upper surface of a substrate, forming gate patterns on an upper surface of the tunnel insulating layer, forming capping layer patterns on sidewalls of the gate patterns and on the upper surface of the tunnel insulating layer, etching a portion of the tunnel insulating layer that is not covered with the gate patterns or the capping layer patterns to form a tunnel insulating layer pattern, and forming a first insulating layer on the upper surface of the substrate to cover the gate patterns, the capping layer patterns, and the tunnel insulating layer pattern, wherein the first insulating layer has an air gap between the capping layer patterns.Type: GrantFiled: November 7, 2014Date of Patent: October 31, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung-Soo Ahn, O Ik Kwon, Bum-Soo Kim, Hyun-Sung Kim, Kyoung-Sub Shin, Min-Kyung Yun, Seung-Pil Chung, Won-Bong Jung
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Publication number: 20170084532Abstract: A vertical memory device includes a substrate, a plurality of channels on the substrate and extending in a vertical direction with respect to a top surface of the substrate, a plurality of non-metal gate patterns surrounding the channels and being stacked on top of each other and spaced apart from each other along the vertical direction, and a plurality of metal gate patterns stacked on top of each other. The metal gate patterns are spaced apart from each other along the vertical direction. Each of the metal gate patterns surrounds a corresponding one of the non-metal gate patterns.Type: ApplicationFiled: September 21, 2016Publication date: March 23, 2017Inventors: Yong-Hoon SON, Cha-Dong YEO, Han-Mei CHOI, Kyung-Hyun KIM, Phil-Ouk NAM, Kwang-Chui PARK, Yeon-Sil SOHN, Jin-I LEE, Won-Bong JUNG
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Publication number: 20170069637Abstract: A nonvolatile memory device includes a conductive line disposed on a substrate and vertically extended from the substrate, a first channel layer disposed on the substrate and vertically extended from the substrate, wherein the first channel layer is spaced apart from the conductive line, a second channel layer vertically extended from the substrate, wherein the second channel layer is disposed between the first channel layer and the conductive line, a first gate electrode disposed between the conductive line and the second channel layer, wherein the first gate electrode includes a first portion having a first thickness and a second portion having a second thickness that is different from the first thickness, and a second gate electrode disposed between the first channel layer and the second channel layer, wherein the second gate electrode has the second thickness.Type: ApplicationFiled: August 30, 2016Publication date: March 9, 2017Inventors: YONG-HOON SON, JONG-WON KIM, CHANG-SEOK KANG, YOUNG-WOO PARK, JAE-DUK LEE, KYUNG-HYUN KIM, BYEONG-JU KIM, PHIL-OUK NAM, KWANG-CHUL PARK, YEON-SIL SOHN, JIN-I LEE, WON-BONG JUNG
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Publication number: 20170033119Abstract: Semiconductor device are provided including a stacked structure having gate electrodes and interlayer insulating layers alternately stacked on a substrate; channel holes extending perpendicular to the substrate through the stacked structure and including channel regions therein; and horizontal parts at lower portions of the stacked structure and including areas in which the channel regions are horizontally elongated from the channel holes. The horizontal parts surround respective channel holes and are connected to each other between at a least portion of the channel holes.Type: ApplicationFiled: May 26, 2016Publication date: February 2, 2017Inventors: Kwang Chul Park, Jang Gn YUN, Won Bong JUNG
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Publication number: 20160358927Abstract: A memory device, including a first memory region including a first substrate, a plurality of first semiconductor devices on the first substrate, and a first interlayer insulating layer covering the plurality of first semiconductor devices; and a second memory region including a second substrate on the first interlayer insulating layer and a plurality of second semiconductor devices on the second substrate, the second substrate including a first region in a plurality of grooves in the first interlayer insulating layer and a second region including grains extending from the first region, the second region being on an upper surface of the first interlayer insulating layer.Type: ApplicationFiled: February 22, 2016Publication date: December 8, 2016Inventors: Phil Ouk NAM, Yong Hoon SON, Kyung Hyun KIM, Byeong Ju KIM, Kwang Chul PARK, Yeon Sil SOHN, Jin I LEE, Jong Heun LIM, Won Bong JUNG
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Publication number: 20160343730Abstract: A vertical memory device includes a substrate, a channel on the substrate, extending in a vertical direction with respect to a top surface of the substrate, and including a protrusion at a lower portion of the channel, the protrusion extending in a parallel direction with respect to the top surface of the substrate, a semiconductor pattern connecting the protrusion and the substrate, and gate lines stacked and spaced apart from each other in the vertical direction, the gate lines on the protrusion and the semiconductor pattern and surrounding the channel.Type: ApplicationFiled: May 16, 2016Publication date: November 24, 2016Inventors: Yong-Hoon Son, Kyung-Hyun KIM, Byeong-Ju KIM, Phil-Ouk NAM, Kwang Chul PARK, Yeon-Sil SOHN, Jin-I LEE, Jong-Heun LIM, Won-Bong JUNG, Kohji KANAMORI
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Publication number: 20150054054Abstract: A method of manufacturing a semiconductor device, the method including forming a tunnel insulating layer on an upper surface of a substrate, forming gate patterns on an upper surface of the tunnel insulating layer, forming capping layer patterns on sidewalls of the gate patterns and on the upper surface of the tunnel insulating layer, etching a portion of the tunnel insulating layer that is not covered with the gate patterns or the capping layer patterns to form a tunnel insulating layer pattern, and forming a first insulating layer on the upper surface of the substrate to cover the gate patterns, the capping layer patterns, and the tunnel insulating layer pattern, wherein the first insulating layer has an air gap between the capping layer patterns.Type: ApplicationFiled: November 7, 2014Publication date: February 26, 2015Inventors: Sung-Soo AHN, O Ik KWON, Bum-Soo KIM, Hyun-Sung KIM, Kyoung-Sub SHIN, Min-Kyung YUN, Seung-Pil CHUNG, Won-Bong JUNG
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Patent number: 8883588Abstract: A method of manufacturing a semiconductor device, the method including forming a tunnel insulating layer on an upper surface of a substrate, forming gate patterns on an upper surface of the tunnel insulating layer, forming capping layer patterns on sidewalls of the gate patterns and on the upper surface of the tunnel insulating layer, etching a portion of the tunnel insulating layer that is not covered with the gate patterns or the capping layer patterns to form a tunnel insulating layer pattern, and forming a first insulating layer on the upper surface of the substrate to cover the gate patterns, the capping layer patterns, and the tunnel insulating layer pattern, wherein the first insulating layer has an air gap between the capping layer patterns.Type: GrantFiled: August 30, 2012Date of Patent: November 11, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Sung-Soo Ahn, O Ik Kwon, Bum-Soo Kim, Hyun-Sung Kim, Kyoung-Sub Shin, Min-Kyung Yun, Seung-Pil Chung, Won-Bong Jung
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Publication number: 20130134496Abstract: A method of manufacturing a semiconductor device, the method including forming a tunnel insulating layer on an upper surface of a substrate, forming gate patterns on an upper surface of the tunnel insulating layer, forming capping layer patterns on sidewalls of the gate patterns and on the upper surface of the tunnel insulating layer, etching a portion of the tunnel insulating layer that is not covered with the gate patterns or the capping layer patterns to form a tunnel insulating layer pattern, and forming a first insulating layer on the upper surface of the substrate to cover the gate patterns, the capping layer patterns, and the tunnel insulating layer pattern, wherein the first insulating layer has an air gap between the capping layer patterns.Type: ApplicationFiled: August 30, 2012Publication date: May 30, 2013Inventors: Sung-Soo AHN, O IK KWON, Bum-Soo KIM, Hyun-Sung KIM, Kyoung-Sub SHIN, Min-Kyung YUN, Seung-Pil CHUNG, Won-Bong JUNG
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Patent number: 7088047Abstract: An inductively coupled plasma generator having a lower aspect ratio reaction gas, comprising a chamber having a gas inlet through which a reaction gas is supplied, a vacuum pump for maintaining the inside of the chamber vacuum and a gas outlet for exhausting the reaction gas after completion of the reaction, a chuck for mounting a target material to be processed inside the chamber, and an antenna to which high-frequency power is applied, the antenna provided at the upper and lateral portions of the chamber, wherein the antenna has parallel antenna elements in which a discharge of a high frequency can be allowed and impedance is low to ensure a low electron temperature, the antenna is disposed such that a powered end of each of the antenna elements and a ground end of each of the antenna elements opposite to the powered end are symmetrical in view of the center of an imaginary circle formed by the antenna to establish rotation symmetry of plasma density profiles, the antenna elements are twisted in a helical mType: GrantFiled: January 26, 2005Date of Patent: August 8, 2006Assignee: Plasmart Co. Ltd.Inventors: Yong-Kwan Lee, Won-Bong Jung, Sang-Won Lee, Sae-Hoon Uhm, Dong-Seok Lee
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Publication number: 20050156530Abstract: An inductively coupled plasma generator having a lower aspect ratio reaction gas, comprising a chamber having a gas inlet through which a reaction gas is supplied, a vacuum pump for maintaining the inside of the chamber vacuum and a gas outlet for exhausting the reaction gas after completion of the reaction, a chuck for mounting a target material to be processed inside the chamber, and an antenna to which high-frequency power is applied, the antenna provided at the upper and lateral portions of the chamber, wherein the antenna has parallel antenna elements in which a discharge of a high frequency can be allowed and impedance is low to ensure a low electron temperature, the antenna is disposed such that a powered end of each of the antenna elements and a ground end of each of the antenna elements opposite to the powered end are symmetrical in view of the center of an imaginary circle formed by the antenna to establish rotation symmetry of plasma density profiles, the antenna elements are twisted in a helical mType: ApplicationFiled: January 26, 2005Publication date: July 21, 2005Inventors: Yong-Kwan Lee, Won-Bong Jung, Sang-Won Lee, Sae-Hoon Uhm, Dong-Seok Lee