Abstract: There is provided a high efficiency ocean thermal difference power generating system by using liquid-vapor ejector and motive pump comprising: an evaporator for changing transferred refrigerant liquid into refrigerant vapor with high temperature and high pressure by the thermal exchange with surface seawater; a vapor-liquid divider which is installed at the outlet part of the evaporator and divides the refrigerants to liquid-state refrigerant and vapor-state refrigerant respectively; a distributor which is installed at the inlet of the evaporator and distributes the refrigerants flowed into the evaporator to multi-paths; a turbine for generating electric power by using the high pressure refrigerant vapor transferred from the liquid-vapor divider or the evaporator; a motive pump for increasing the pressure of the refrigerant liquid distributed from the distributor or the liquid-vapor divider; a liquid-vapor ejector for mixing the low pressure refrigerant vapor which passed the turbine and the high pressure ref

Abstract: A method of operating a semiconductor memory device includes applying a program pulse at least once to each of a plurality of pages; performing a pre-read operation on a reference page among the plurality of pages through an initial test voltage; repeating the pre-read operation by controlling the initial test voltage until a result of the pre-read operation is a pass; setting the initial test voltage of when the result of the pre-read operation is the pass as a reference test voltage; and detecting a defective page among the plurality of pages by performing read operations on the plurality of pages through the reference test voltage.

Abstract: The present invention relates to a method for producing graphene on a face-centered cubic metal catalyst having a plane oriented in one direction, and more particularly to a method of producing graphene on a metal catalyst having the (100) or (111) crystal structure and a method of producing graphene using a catalyst metal foil having a single orientation, obtained by electroplating a metal catalyst by a pulse wave current and annealing the metal catalyst. The invention also relates to a method of producing graphene using a metal catalyst, and more particularly to a method of producing graphene, comprising the steps of: alloying a metal catalyst with an alloying element; forming step structures on the metal catalyst substrate in an atmosphere of a gas having a molecular weight of carbon; and supplying hydrocarbon and hydrogen gases to the substrate. On unidirectionally oriented metal catalyst prepared according to the present invention, graphene can be grown uniformly and epitaxially.

Abstract: A nonvolatile memory device includes a plurality of memory blocks. The nonvolatile memory device includes a controller configured to perform an erase operation by repeating an erase loop, and generates and stores a test result based on a pass erase loop count of the erase operation in response to a result processing command. The erase loop includes applying an erase voltage to a target memory block among the memory blocks in response to an erase command.

Abstract: The present invention relates to a method for producing graphene on a face-centered cubic metal catalyst having a plane oriented in one direction, and more particularly to a method of producing graphene on a metal catalyst having the (100) or (111) crystal structure and a method of producing graphene using a catalyst metal foil having a single orientation, obtained by electroplating a metal catalyst by a pulse wave current and annealing the metal catalyst. The invention also relates to a method of producing graphene using a metal catalyst, and more particularly to a method of producing graphene, comprising the steps of: alloying a metal catalyst with an alloying element; forming step structures on the metal catalyst substrate in an atmosphere of a gas having a molecular weight of carbon; and supplying hydrocarbon and hydrogen gases to the substrate. On unidirectionally oriented metal catalyst prepared according to the present invention, graphene can be grown uniformly and epitaxially.

Abstract: A semiconductor memory device may include: a memory cell array comprising: a Content Addressable Memory (CAM) cell block including CAM cells storing option Information including operation setting information for controlling an operation of the semiconductor memory device, and error check information for the operation setting information; and memory blocks including memory cells for storing data; an error detection unit suitable for reading out, in response to a CAM read command, the operation setting information and the error check information stored in the CAM cell block and outputting an error detection signal indicating whether there is an error; and a control logic suitable for determining and outputting a state of a ready/busy signal depending on the error detection signal.

Abstract: A method for controlling a hybrid vehicle is provided. The method includes setting a driving path of the vehicle based on an input destination and current position and predicting a future speed of the vehicle using information regarding the driving path, environmental information, and driving pattern information of a driver. An optimum power distribution map is derived including an optimum SOC trajectory and a power distribution ratio of the engine and the motor using the predicted future speed. Additionally, engine power and motor power is distributed using the optimum SOC trajectory and a power distribution ratio of the engine and the motor.

Abstract: A depth pixel of a three-dimensional image sensor includes a first photo gate which is turned on/off in response to a first photo control signal, a first photo detection area configured to generate first charges based on a received light reflected from a subject when the first photo gate is turned on, a first transmission gate which is turned on/off in response to a first transmission control signal, a first floating diffusion area configured to accumulate the first charges generated from the first photo detection area when the first transmission gate is turned on, and a first compensation unit configured to generate second charges which are different from the first charges based on ambient light components included in the received light to supply the second charges to the first floating diffusion area.

Abstract: An error correction circuit includes: a failure detection unit suitable for detecting failed data among a plurality of data; a data output control unit suitable for selectively outputting test data corresponding to a predetermined amount of data excluding the failed data; and an error correction unit suitable for performing a unit ECC operation on the test data.

Abstract: A method for controlling a hybrid vehicle is provided. The method includes setting a driving path of the vehicle based on an input destination and current position and predicting a future speed of the vehicle using information regarding the driving path, environmental information, and driving pattern information of a driver. An optimum power distribution map is derived including an optimum SOC trajectory and a power distribution ratio of the engine and the motor using the predicted future speed. Additionally, engine power and motor power is distributed using the optimum SOC trajectory and a power distribution ratio of the engine and the motor.

Abstract: There is provided a high efficiency ocean thermal difference power generating system by using liquid-vapor ejector and motive pump comprising: an evaporator for changing transferred refrigerant liquid into refrigerant vapor with high temperature and high pressure by the thermal exchange with surface seawater; a vapor-liquid divider which is installed at the outlet part of the evaporator and divides the refrigerants to liquid-state refrigerant and vapor-state refrigerant respectively; a distributor which is installed at the inlet of the evaporator and distributes the refrigerants flowed into the evaporator to multi-paths; a turbine for generating electric power by using the high pressure refrigerant vapor transferred from the liquid-vapor divider or the evaporator; a motive pump for increasing the pressure of the refrigerant liquid distributed from the distributor or the liquid-vapor divider; a liquid-vapor ejector for mixing the low pressure refrigerant vapor which passed the turbine and the high pressure ref

Abstract: An error correction circuit includes: a failure detection unit suitable for detecting failed data among a plurality of data; a data output control unit suitable for selectively outputting test data corresponding to a predetermined amount of data excluding the failed data; and an error correction unit suitable for performing a unit ECC operation on the test data.

Abstract: Systems, methods and fabrication processes relating to dynamic random access memory (DRAM) devices involving data signals grouped into 10 bits are disclosed. According to one illustrative implementation a DRAM device may comprise a memory core, circuitry that receives a data bus inversion (DBI) bit associated with a data signal as input directly, without transmission through DBI logic associated with an input buffer, circuitry that stores the DBI bit into the memory core, reads the DBI bit from the memory core, and provides the DBI bit as output. In further implementations, DRAM devices herein may store and process the DBI bit on an internal data bus as a regular data bit.

Abstract: A method of operating a semiconductor memory device includes applying a program pulse at least once to each of a plurality of pages; performing a pre-read operation on a reference page among the plurality of pages through an initial test voltage; repeating the pre-read operation by controlling the initial test voltage until a result of the pre-read operation is a pass; setting the initial test voltage of when the result of the pre-read operation is the pass as a reference test voltage; and detecting a defective page among the plurality of pages by performing read operations on the plurality of pages through the reference test voltage.

Abstract: A nonvolatile memory device may include a plurality of memory blocks. The nonvolatile memory device may include a controller configured to perform an erase operation by repeating an erase loop, and may generate and store a test result based on a pass erase loop count of the erase operation in response to a result processing command. The erase loop may include applying an erase voltage to a target memory block among the memory blocks in response to an erase command.

Abstract: Disclosed is a rangefinder comprising: a housing shaped like a cylinder and opened frontward and backward; an object lens comprising one or more lenses arranged in a front end portion of the housing and facing an object targeted for distance measurement; a display providing a user with an image from the object lens; an image split prism arranged in between the object lens and the display, making the image from the object lens be split and focused, and installed movably along an optical axis within the housing so that a space between split images can be adjusted; and a distance indicator indicating distance from the targeted object in accordance with positions of the image split prism, in a state that the position of the image split prism is adjusted to set up the space between the split images to a reference position.

Abstract: Systems, methods and fabrication processes relating to dynamic random access memory (DRAM) devices involving data signals grouped into 10 bits are disclosed. According to one illustrative implementation a DRAM device may comprise a memory core, circuitry that receives a data bus inversion (DBI) bit associated with a data signal as input directly, without transmission through DBI logic associated with an input buffer, circuitry that stores the DBI bit into the memory core, reads the DBI bit from the memory core, and provides the DBI bit as output. In further implementations, DRAM devices herein may store and process the DBI bit on an internal data bus as a regular data bit.

Abstract: An image sensor according to an example embodiment of includes a first pixel and a second pixel in a first row. The first pixel includes a first photoelectric conversion element at a first depth in a semiconductor substrate and the first photoelectric conversion element is configured to convert a first visible light spectrum into a first photo charge, and the second pixel includes a second photoelectric conversion element at a second depth from the first depth in the semiconductor substrate, the second photoelectric conversion element is at least partially overlapped by the first photoelectric conversion element in a vertical direction, and the second photoelectric conversion element is configured to convert a second visible light spectrum into a second photo charge.

Abstract: Disclosed are an oxide-coated metal catalyst for a composite electrode and a method for preparing a composite electrode using the same. The metal catalyst includes oxide particles applied thereto, wherein the oxide particles are applied so as not to overlap one another or are applied as an independent separate layer, and the oxide particles are nanograins having a diameter of 1-500 nm. The oxide applied to the metal catalyst prevents the agglomeration of particles of the metal catalyst even under high-temperature conditions. Accordingly, the present invention overcomes the problem in which particles of a metal catalyst that is used in the anode or cathode of various fuel cells or in various electrode materials agglomerate when the metal catalyst particles reach high-temperature conditions during the fabrication or operation of the fuel cells, thereby reducing the efficiency of the electrode.

Abstract: A depth pixel of an image sensor includes a depth sensing element configured to generate first charges that are photo-electrically converted from a light reflected from an object, a first floating diffusion node configured to receive the first charges from the depth sensing element, a second floating diffusion node configured to output second charges corresponding to a component of a reflection light where a component of an ambient light is cancelled, and an ambient light cancellation circuit configured to detect the ambient light to control a barrier level of a charge transfer path between the first floating diffusion node and the second floating diffusion node in response to the ambient light.