Abstract: A high voltage connector for a vehicle may include a male connector having a truncated conical protuberance-shaped first terminal, and a female connector having a second terminal provided with a truncated conical coupling groove corresponding to the first terminal, wherein an electrical connection between the male connector and the female connector is accomplished as the first terminal is inserted into the coupling groove of the second terminal. When the first terminal and the second terminal are coupled to each other, elastic deformation may be induced which may provide a holding force between the first and second terminals using elastic stress, resulting in improved stability of a high voltage power supply.

Abstract: A method of a transmitting node may comprise: modulating a codeword corresponding to data to be transmitted; generating sparse space-frequency block code (SSFBC)-coded symbols by encoding the modulated codeword in an SSFBC scheme; performing precoding on the SSFBC-coded symbols for each of subbands respectively corresponding to transmit antenna groups; and transmit the precoded SSFBC-coded symbols by performing beamforming on the precoded SSFBC-coded symbols using at least one array antenna group among two or more array antenna groups.

Abstract: An operation method of a first communication apparatus may include: identifying one or more synchronization signal components constituting a synchronization signal component set; generating a plurality of synchronization signal sections based on the one or more synchronization signal components and a plurality of primary coefficients corresponding to the one or more synchronization signal components; generating one or more synchronization signal parts based on a combination of the plurality of synchronization signal sections; generating one or more synchronization signals based on a combination of the one or more synchronization signal parts in time domain; and transmitting the generated one or more synchronization signals.

Abstract: An operation method of a first communication node in a communication system may include: generating a base sequence; performing a quadrature phase shift keying (QPSK) operation on the base sequence; generating a first signal sequence by performing a rotational transform operation by a first angle on a complex plane with respect to a result of the QPSK operation; modulating the first signal sequence to generate first modulation symbols; and transmitting a first signal composed of the first modulation symbols to a second communication node, wherein each of a plurality of elements constituting the first signal sequence has a real value or a pure imaginary value.

Abstract: A capacitor for a semiconductor device is disclosed with increased capacitance which is produced by a simplified manufacturing process. The capacitor has a storage node electrode structure formed on the semiconductor device having impurity regions formed therein. The storage node electrode structure includes a buried layer formed in a storage node hole defined by the semiconductor device, the buried layer being in contact with at least one impurity region, a bottom layer formed on the buried layer and extending beyond the buried layer, a first cylindrical electrode having first walls upwardly extending from the bottom layer, and second cylindrical electrodes having second walls upwardly extending from the bottom layer and disposed on outer sides of the first cylindrical electrode.

Abstract: A capacitor for a semiconductor device is disclosed with increased capacitance which is produced by a simplified manufacturing process. The capacitor has a storage node electrode structure formed on the semiconductor device having impurity regions formed therein. The storage node electrode structure includes a buried layer formed in a storage node hole defined by the semiconductor device, the buried layer being in contact with at least one impurity region, a bottom layer formed on the buried layer and extending beyond the buried layer, a first cylindrical electrode having first walls upwardly extending from the bottom layer, and second cylindrical electrodes having second walls upwardly extending from the bottom layer and disposed on outer sides of the first cylindrical electrode.

Abstract: A capacitor for a semiconductor device is disclosed with increased capacitance which is produced by a simplified manufacturing process. The capacitor has a storage node electrode structure formed on the semiconductor device having impurity regions formed therein. The storage node electrode structure includes a buried layer formed in a storage node hole defined by the semiconductor device, the buried layer being in contact with at least one impurity region, a bottom layer formed on the buried layer and extending beyond the buried layer, a first cylindrical electrode having first walls upwardly extending from the bottom layer, and second cylindrical electrodes having second walls upwardly extending from the bottom layer and disposed on outer sides of the first cylindrical electrode.

Abstract: A capacitor for a semiconductor device is disclosed with increased capacitance which is produced by a simplified manufacturing process. The capacitor has a storage node electrode structure formed on the semiconductor device having impurity regions formed therein. The storage node electrode structure includes a buried layer formed in a storage node hole defined by the semiconductor device, the buried layer being in contact with at least one impurity region, a bottom layer formed on the buried layer and extending beyond the buried layer, a first cylindrical electrode having first walls upwardly extending from the bottom layer, and second cylindrical electrodes having second walls upwardly extending from the bottom layer and disposed on outer sides of the first cylindrical electrode.

Abstract: A capacitor for a semiconductor device is disclosed with increased capacitance which is produced by a simplified manufacturing process. The capacitor has a storage node electrode structure formed on the semiconductor device having impurity regions formed therein. The storage node electrode structure includes a buried layer formed in a storage node hole defined by the semiconductor device, the buried layer being in contact with at least one impurity region, a bottom layer formed on the buried layer and extending beyond the buried layer, a first cylindrical electrode having first walls upwardly extending from the bottom layer, and second cylindrical electrodes having second walls upwardly extending from the bottom layer and disposed on outer sides of the first cylindrical electrode.

Abstract: Capacitor and method for fabricating the same, which can simplify a fabrication process and reduce parasitic capacitances between signal lines, the capacitor including a first insulating layer formed on a substrate, a bitline patterned on the first insulating layer, a second insulating layer formed on the bitline, a first electrode formed on the second insulating layer with slopes at both sides, a dielectric film formed on the first electrode, a node contact formed on one side of the first electrode and in contact with the substrate, and a second electrode formed on the dielectric film and connected with the node contact electrically, and the method including the steps of (1) forming a first insulating layer on a substrate, and patterning a bitline on the first insulating layer, (2) forming a second insulating layer on an entire surface inclusive of the bitline, (3) depositing a first conductive material on the second insulating layer, (4) etching the first conductive material to form a first electrode with a

Abstract: The interconnect structure for semiconductor devices includes a semiconductor substrate, an insulating layer on the semiconductor substrate, a first back-up layer on the insulating layer, a first conductive layer on the first back-up layer, a second back-up layer on the first conductive layer, a second conductive layer on the second back-up layer, and a third back-up layer on the second conductive layer. The first and second conductive layers are formed of aluminum-based alloys, and the first to third back-up layers are formed of aless conductive material such as transition metal alloys.

Abstract: A capacitor for a semiconductor device is disclosed with increased capacitance which is produced by a simplified manufacturing process. The capacitor has a storage node electrode structure formed on the semiconductor device having impurity regions formed therein. The storage node electrode structure includes a buried layer formed in a storage node hole defined by the semiconductor device, the buried layer being in contact with at least one impurity region, a bottom layer formed on the buried layer and extending beyond the buried layer, a first cylindrical electrode having first walls upwardly extending from the bottom layer, and second cylindrical electrodes having second walls upwardly extending from the bottom layer and disposed on outer sides of the first cylindrical electrode.

Abstract: Capacitor and method for fabricating the same, which can simplify a fabrication process and reduce parasitic capacitances between signal lines, the capacitor including a first insulating layer formed on a substrate, a bitline patterned on the first insulating layer, a second insulating layer formed on the bitline, a first electrode formed on the second insulating layer with slopes at both sides, a dielectric film formed on the first electrode, a node contact formed on one side of the first electrode and in contact with the substrate, and a second electrode formed on the dielectric film and connected with the node contact electrically, and the method including the steps of (1) forming a first insulating layer on a substrate, and patterning a bitline on the first insulating layer, (2) forming a second insulating layer on an entire surface inclusive of the bitline, (3) depositing a first conductive material on the second insulating layer, (4) etching the first conductive material to form a first electrode with a

Abstract: Capacitor and method for fabricating the same, which can simplify a fabrication process and reduce parasitic capacitances between signal lines, the capacitor including a first insulating layer formed on a substrate, a bitline patterned on the first insulating layer, a second insulating layer formed on the bitline, a first electrode formed on the second insulating layer with slopes at both sides, a dielectric film formed on the first electrode, a node contact formed on one side of the first electrode and in contact with the substrate, and a second electrode formed on the dielectric film and connected with the node contact electrically, and the method including the steps of (1) forming a first insulating layer on a substrate, and patterning a bitline on the first insulating layer, (2) forming a second insulating layer on an entire surface inclusive of the bitline, (3) depositing a first conductive material on the second insulating layer, (4) etching the first conductive material to form a first electrode with a

Abstract: A capacitor for a semiconductor device is disclosed with increased capacitance which is produced by a simplified manufacturing process. The capacitor has a storage node electrode structure formed on the semiconductor device having impurity regions from therein. The storage node electrode structure includes a buried layer formed in a storage node hole defined by the semiconductor device, the buried layer being in contact with at least one impurity region, a bottom layer formed on the buried layer and extending beyond the buried layer, a first cylindrical electrode having first walls upwardly extending from the bottom layer, and second cylindrical electrodes having second walls upwardly extending from the bottom layer and disposed on outer sides of the first cylindrical electrode.