Abstract: A semiconductor package may include a substrate, a chip structure on the substrate, a connection pad on the substrate, a connection sheet on the connection pad, and a connection wire electrically connecting the chip structure and the substrate, the connection pad and the connection sheet may include the same material, and a grain boundary may be formed between the connection sheet and the connection pad.

Abstract: A surface mount technology (SMT) package includes an SMT substrate including an interconnection layer, an insulating layer having an arrangement region for the interconnection layer, and a mask layer on an upper surface of the insulating layer, a component including an insulating body, and an external electrode having at least a portion on a surface of the insulating body opposing the SMT substrate, and a solder that electrically connects the interconnection layer and the external electrode to each other. The mask layer has an opening, and the SMT substrate further includes an insulating support that supports the external electrode in the opening such that the external electrode is spaced apart from the interconnection layer and the insulating layer.

Abstract: A semiconductor device may include a substrate, a pad on the substrate and connected to an interconnection pattern in the substrate, and a solder resist layer on the substrate, the solder resist layer having an opening exposing the pad. A top surface of the pad having a center region, and a peripheral region surrounding the center region. The center region of the top surface of the pad may be located at a level different from the peripheral region of the top surface of the pad, and a first width of the pad may be constant regardless of a distance from the substrate.

Abstract: A semiconductor package includes: a redistribution substrate; a frame including first and second vertical connection conductors, and having a through-hole; first and second semiconductor chips; an encapsulant; a second redistribution structure disposed on the encapsulant, a conductive wire electrically connecting the second semiconductor chip and the second vertical connection conductor; and a vertical connection via penetrating a portion of the encapsulant, and electrically connecting the second redistribution structure and the first vertical connection conductor. The first semiconductor chip is connected to the second vertical connection conductor by the first redistribution structure.

Abstract: A display module and a method for manufacturing thereof are provided. The display module includes a substrate including a pad, a conduction film which is bonded to the substrate including the pad, wherein at least one of a surface of the conduction film and an inner portion of the conduction film is black color treated, and a display device mounted on the pad to which the conduction film is bonded.

Abstract: According to various embodiments, provided is an electrical element transfer apparatus comprising: a fixing jig in which each of a plurality of electrical elements is arranged at a predetermined interval; a movement jig movably arranged at an upper part of the fixing jig, and including a plurality of first accommodating grooves for accommodating at least a part of each of the plurality of electrical elements; and an attraction device arranged around the movable jig and attaching each of the plurality of electrical elements through the movable jig to the first accommodating groove of the movable jig through magnetic force. Additional various embodiments are possible.

Abstract: The disclosure describes a micro Light Emitting Diode (LED) display. The display may include a Printed Circuit Board (PCB) including a plurality of solder pads, a micro LED package including a plurality of micro LED chips, and a plurality of solder electrodes which bond the micro LED chips onto the solder pads of the PCB. The micro LED package may be re-arranged in an Red Green Blue (RGB) state on a temporary fixing film by using a pickup device in accordance with a display pixel configuration, after the micro LED chips are attached to a carrier film.

Abstract: A semiconductor package includes: a redistribution substrate; a frame including first and second vertical connection conductors, and having a through-hole; first and second semiconductor chips; an encapsulant; a second redistribution structure disposed on the encapsulant, a conductive wire electrically connecting the second semiconductor chip and the second vertical connection conductor; and a vertical connection via penetrating a portion of the encapsulant, and electrically connecting the second redistribution structure and the first vertical connection conductor. The first semiconductor chip is connected to the second vertical connection conductor by the first redistribution structure.

Abstract: A semiconductor package includes: a redistribution substrate; a frame including first and second vertical connection conductors, and having a through-hole; first and second semiconductor chips; an encapsulant; a second redistribution structure disposed on the encapsulant, a conductive wire electrically connecting the second semiconductor chip and the second vertical connection conductor; and a vertical connection via penetrating a portion of the encapsulant, and electrically connecting the second redistribution structure and the first vertical connection conductor. The first semiconductor chip is connected to the second vertical connection conductor by the first redistribution structure.

Abstract: A display module and a method for manufacturing thereof are provided. The display module includes a substrate including a pad, a conduction film which is bonded to the substrate including the pad, wherein at least one of a surface of the conduction film and an inner portion of the conduction film is black color treated, and a display device mounted on the pad to which the conduction film is bonded.

Abstract: The disclosure describes a micro Light Emitting Diode (LED) display. The display may include a Printed Circuit Board (PCB) including a plurality of solder pads, a micro LED package including a plurality of micro LED chips, and a plurality of solder electrodes which bond the micro LED chips onto the solder pads of the PCB. The micro LED package may be re-arranged in an Red Green Blue (RGB) state on a temporary fixing film by using a pickup device in accordance with a display pixel configuration, after the micro LED chips are attached to a carrier film.

Abstract: A semiconductor package includes: a connection structure having first and second surfaces opposing each other and including a redistribution layer; a semiconductor chip disposed on the first surface of the connection structure and having connection pads connected to the redistribution layer; an encapsulant disposed on the first surface of the connection structure, encapsulating the semiconductor chip, and including an opaque or translucent resin; a mark indicating identification information and carved in the encapsulant; and a passivation layer disposed on the encapsulant and including a transparent resin.

Abstract: A semiconductor package includes: a redistribution substrate; a frame including first and second vertical connection conductors, and having a through-hole; first and second semiconductor chips; an encapsulant; a second redistribution structure disposed on the encapsulant, a conductive wire electrically connecting the second semiconductor chip and the second vertical connection conductor; and a vertical connection via penetrating a portion of the encapsulant, and electrically connecting the second redistribution structure and the first vertical connection conductor. The first semiconductor chip is connected to the second vertical connection conductor by the first redistribution structure.

Abstract: According to various embodiments, provided is an electrical element transfer apparatus comprising: a fixing jig in which each of a plurality of electrical elements is arranged at a predetermined interval; a movement jig movably arranged at an upper part of the fixing jig, and including a plurality of first accommodating grooves for accommodating at least a part of each of the plurality of electrical elements; and an attraction device arranged around the movable jig and attaching each of the plurality of electrical elements through the movable jig to the first accommodating groove of the movable jig through magnetic force. Additional various embodiments are possible.

Abstract: A fan-out semiconductor package includes: a frame, including a wiring layer, and having a through-hole; a semiconductor chip disposed in the through-hole, and including a connection pad; an encapsulant covering at least a portion of each of the frame and an inactive surface of the semiconductor chip, and having a first opening exposing at least a portion of the wiring layer; an insulating layer disposed on the encapsulant, and having a second opening formed in the first opening to expose at least a portion of the wiring layer; a conductive pattern layer disposed on the insulating layer; a conductive via disposed in the second opening; and a connection structure disposed on the frame and an active surface of the semiconductor chip, and including one or more redistribution layers. The conductive pattern layer and the redistribution layer are electrically connected to the connection pad.

Abstract: A semiconductor package includes: a connection structure having first and second surfaces opposing each other and including a redistribution layer; a semiconductor chip disposed on the first surface of the connection structure and having connection pads connected to the redistribution layer; an encapsulant disposed on the first surface of the connection structure, encapsulating the semiconductor chip, and including an opaque or translucent resin; a mark indicating identification information and carved in the encapsulant; and a passivation layer disposed on the encapsulant and including a transparent resin.

Abstract: A fan-out semiconductor package includes: a frame, including a wiring layer, and having a through-hole; a semiconductor chip disposed in the through-hole, and including a connection pad; an encapsulant covering at least a portion of each of the frame and an inactive surface of the semiconductor chip, and having a first opening exposing at least a portion of the wiring layer; an insulating layer disposed on the encapsulant, and having a second opening formed in the first opening to expose at least a portion of the wiring layer; a conductive pattern layer disposed on the insulating layer; a conductive via disposed in the second opening; and a connection structure disposed on the frame and an active surface of the semiconductor chip, and including one or more redistribution layers. The conductive pattern layer and the redistribution layer are electrically connected to the connection pad.

Abstract: Provided herein is technology relating to enzymatic modification of nucleic acids and particularly, but not exclusively, to methods and compositions relating to using uracil-DNA-N-glycosylase for minimizing or eliminating errors in a DNA sequence due to deamination of cytosine residues.

Abstract: Disclosed herein is a semiconductor package capable of stably implementing an interlayer bonding of a stacked board, the semiconductor package includes: a lower package having a chip module mounted thereon so as to be connected to a circuit pattern; an upper package stacked on the lower package and having an electrical device mounted thereon; and a bump receiving a tip of a solder ball electrically connecting the lower package and the upper package and coupled to the solder ball.

Abstract: Provided herein is technology relating to enzymatic modification of nucleic acids and particularly, but not exclusively, to methods and compositions relating to using uracil-DNA-N-glycosylase for minimizing or eliminating errors in a DNA sequence due to deamination of cytosine residues.