Abstract: A device for preventing a human body from being jammed by using a change in capacitance, includes: a sensor unit which detects a change in capacitance corresponding to a gap between an external conductor pressed by a human body approaching a driven object and an internal conductor; a signal processing unit which compares a detection signal of the sensor unit with a reference value and outputs a jamming occurrence signal indicating the human body being jammed in the driven object; a motor driving unit which drives a motor to move the driven object; and a control unit which controls the motor driving unit to stop or move the driven object in the opposite direction when the jamming occurrence signal is received from the signal processing unit, thereby preventing a safety accident caused by the human body being jammed.

Abstract: A non-contact-type pinch prevention device suppressing the distortion of reception signals, caused by noise around an anti-pinch strip, to increase the reliability of a sensing operation for detecting a human body comprises: an anti-pinch strip which includes first and second lead wires buried in a strip body to be spaced from each other, and which allows the first lead wire to receive and output a sensing signal radiated through the second lead wire; a sensor board, which is connected to the first and second lead wires of the anti-pinch strip, generates the sensing signal in the second lead wire, and determines whether the human body is detected, according to the signal received by the first lead wire; and a control unit for performing a control operation corresponding to a body pinch situation according to a determination signal of the sensor board.

Abstract: Provided is a CMOS exponential function generating circuit capable of compensating for the exponential function characteristic according to temperature variations. The exponential function generating circuit includes an voltage scaler scaling the value of an external gain control voltage signal, an exponential function generating unit generating exponential function current and voltage in response to a signal output from the voltage scaler, a reference voltage generator providing a reference voltage to the exponential function generating unit, and a temperature compensator compensating for the exponential function characteristic according to temperature variations.

Abstract: A device and method of eliminating the interference to a voice command from the sound from the speaker, thereby improving the success rate of speech recognition even in the presence of the direct and echoed sound.

Abstract: The present invention relates to a tuning circuit, more specifically to a tuning circuit for continuous-time filter capable of making exact the Gm value to minimize the variation of the cutoff frequency due to the variation of process in the Gm-C type of continuous-time filter.

Abstract: A CMOS high frequency variable gain amplifier with maximum high frequency operation and wide variable gain characteristics that is formed from an amplifier having a plurality of variable gain amplifier cells connected in series for continuously enabling wide gain variation; and a control voltage generator for generating and outputting the control voltage of the variable gain amplifier cells. By using both the saturation region and the linear region of input differential transistors constituting the variable gain amplifier cells in order to obtain wide gain variation characteristics, it is possible for the variable gain amplifier to operate in the saturation region when the input signal is small to obtain a high gain and to operate in the linear region when the input signal is large to obtain minimum distortion and a low gain. Also, it is possible for the gain to have the characteristics in the form of an exponential function to the gain control voltage.

Abstract: The present invention discloses a mixer using a replica voltage-current converter, and more particularly a mixer using the replica voltage-current (V-I) converter of the present invention, which feedbacks the output current of the replica voltage-current converter using an additional amplifier so as to improve the linearity thereof by the gain of the amplifier because the conventional mixer operating at a high speed dissipates a lot of electrical power to have low output impedance.

Abstract: Disclosed is a multiple feedback loop ring oscillator and delay cell with high oscillation voltage. It is an object of the present invention to implement a new ring oscillator for the VCO of a high speed PLL and a proper delay cell with a high speed and low noise. The apparatus is composed of multiple feedback loop ring oscillator that 4 delay cells which have the first main input stage, the second main input stage, the first subsidiary input stage, the second subsidiary input stage, the third subsidiary input stage, the forth subsidiary input stage, the first output stage and the second output stage is connected to the main loop and subsidiary loop. The present invention has advantages that it can be operated in high speed, it has a low power sensitivity, there is no power noise because there is no variation of a supply current and it can improve noise characteristics.

Abstract: There is disclosed a low frequency filter. A low frequency cutoff filter includes a filter circuit having a capacitor connected between an input terminal and an output terminal and an active resistor connected to the output terminal, having a very large resistance, and a bias circuit having a negative feedback to set a biasing voltage of the active resistor to a desired value, thereby implementing the cutoff filter within a semiconductor chip as one set with the capacitor having a small capacitance. A low frequency pass filter includes an active resistor having a very large resistance, means for setting a biasing voltage of the active resistor to a desired value, and a capacitor connected between the output terminal and the ground. Therefore, the low pass filter can be integrated-circuited using even small capacitor.

Abstract: A double mode modulator, particularly, for a portable telephone, which is adapted to realize both digital and analog modulations and have a low phase noise and a reduced locking time with a device readily integrated in an integrated circuit, including: a frequency synthesizer for synthesizing a particular frequency from an external reference clock signal; a digital modulator for performing a quadrature modulation for an output signal of the frequency synthesizer; and an analog modulator for performing a frequency modulation for the output signal of the frequency synthesizer.

Abstract: The present invention relates to a high voltage driving circuit for preventing an transient current. The high voltage driving circuit including a non-overlap signal generator for generating the first and second non-overlap signals in response to the logic level signal, a satge for generating a first driving signal in response to the logic level signal and the first and second non-overlap signals, a pre-driving circuit which is driven in response to the first non-overlap signal and the first driving signal, and a complementary output circuit for controlling a current flowing toward the output terminal in response to the output signal of the pre-driving circuit and the second non-overlap signal.

Abstract: A CMOS offset trimming circuit and offset generation circuit for obtaining the corrected optimum offset value for correcting the offset generated in the CMOS analog circuit. An offset trimming circuit comprises a flip-flop for loading a data to be used for obtaining an optimum offset value or a data to be trimmed according to an input clock, a fuse circuit for setting the circuit with a corrected optimum offset value obtained in a corresponding mode by receiving the data loaded on the flip-flop and the mode selection signal as an input signal, and a selection logic circuit for outputting a selected signal as a trimming output signal by selecting one from the group consisting of the data loaded on the flip-flop and the data output from the fuse circuit according to the operation mode.

Abstract: An integrated circuit built-in type power delay circuit which is capable of supplying a stable supply power to each circuit of the integrated circuit by generating a supply power control signal voltage after a predetermined time. The circuit includes a receiving unit for receiving a supply voltage VDD and charging the same, a supplying unit for supplying a current, an inverting unit for inverting an output value from the charging unit, a switching unit controlled in accordance with an output value from the inverting unit for switching an output from the current supply unit, a current regenerating unit for receiving a control of the switching unit and discharging an output value from the charging unit, an electric potential value conversion unit controlled by an output value from the inverting unit for converting an output value from the charging unit into a low level, and a buffering unit for receiving an output value from the inverting unit for buffering the output value and outputting a non-inverted signal.

Abstract: An improved data retiming circuit which is capable of more effectively retiming an externally inputted data by using a plurality of clocks from a voltage controlled oscillator of a phase-locked loop.

Abstract: The present invention relates to a fault detection and automatic recovery apparatus of write-read pointers in FIFO. While storing effective data in a register in writing performance, the apparatus does not unconditionally enable a FULL.sub.-- FLAG signal allotted to the register but confirms the relation of write-read pointers at that time and the EMPTY.sub.-- FLAG signal of a register at which the read pointer is situated and detects the error of FIFO. By selectively enabling the FULL.sub.-- FLAG signal of the register according to the result of detection, it automatically restores the FIFO functions without unnecessary re-initialization or the discontinuation of data transmission attributable thereto.

Abstract: A voltage control oscillation circuit for a CMOS which is capable of reducing phase noise and power consumption by adapting a voltage amplitude control loop and a common mode feedback circuit to a conventional LC-tank circuit. The circuit includes an LC-tank oscillation unit for outputting an oscillation voltage, an output common mode feedback unit for receiving an output from the LC-tank oscillation unit and eliminating a common mode noise of the output, and a voltage amplitude control unit for controlling a bias current of the LC-tank oscillation unit in accordance with a voltage difference at both ends of an LC-tank oscillation terminal which voltage is applied thereto through the output common mode feedback unit, for thus controlling the amount of an oscillation voltage.

Abstract: A low power output buffer circuit for outputting an Emitter Coupled Logic(ECL) signal or Pseudo ECL(PECL) signal using a CMOS device is disclosed. The prior art differential output buffer circuit is comprised of two independent output buffer circuits and each output buffer circuit utilizes 50 ohms of the load resistors, having 20 mW of current to be applied to the circuit, which requires 100 mW of total consumptive power to operate the entire circuit. According to the present invention, a simplified output buffer circuit can be constructed by connecting 100 ohms of load resistors having a center tap to ground to two pads, which reduces half of the consumptive power as compared to that in the prior art circuit.

Abstract: A capacitor type voltage divider circuit is disclosed. The divider has a plurality of reference voltage signals applied from an external source. A plurality of switching sections are provided for switching the reference voltage signals from the source in response to first and second clock signals. A plurality of dividing sections are provided which are each comprised of two capacitors for dividing the voltage signals from the switching section into a predetermined value. With the dividing circuit, precise levels of reference voltage signals are obtained and power consumption is low without an increase in size or lowering of operational speed.

Abstract: Disclosed is a low power-consumption type comparator circuit having two input terminals for receiving two input signals, one of which is an input reference signal and the other of which is an input comparison signal, and two output terminals, the circuit comprising signal converting portion for converting the input signals into current signals, respectively; switching portion for controlling transmission of the current signals to output terminals of the circuit in response to a latch signal indicating a latch operation or a normal operation of the circuit; high level holding portion for maintaining each voltage level of the output terminals to a logical high-state only when the latch operation of the circuit is not performed; amplifying/determining portion for amplifying the current signals and determining logical level of the input comparison signal; and output feedback portion for receiving output signals of the output terminals and enabling to make a current flowing in the circuit to a zero-state, only whi