Patents by Inventor Won-gi Chang

Won-gi Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11289430
    Abstract: A semiconductor package may include a package substrate, a support structure on the package substrate and having a cavity therein, and at least one first semiconductor chip on the package substrate in the cavity. The support structure may have a first inner sidewall facing the cavity, a first top surface, and a first inclined surface connecting the first inner sidewall and the first top surface. The first inclined surface may be inclined with respect to a top surface of the at least one first semiconductor chip.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: March 29, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-Gi Chang, Bok Sik Myung
  • Publication number: 20210050309
    Abstract: A semiconductor package may include a package substrate, a support structure on the package substrate and having a cavity therein, and at least one first semiconductor chip on the package substrate in the cavity. The support structure may have a first inner sidewall facing the cavity, a first top surface, and a first inclined surface connecting the first inner sidewall and the first top surface. The first inclined surface may be inclined with respect to a top surface of the at least one first semiconductor chip.
    Type: Application
    Filed: March 31, 2020
    Publication date: February 18, 2021
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Won-Gi CHANG, Bok Sik MYUNG
  • Patent number: 10923465
    Abstract: A method for manufacturing a semiconductor device includes stacking, on a package substrate, first semiconductor chips. Each of the first semiconductor chips includes a first adhesive film. The method includes stacking, respectively on the first semiconductor chips, second semiconductor chips. Each of the second semiconductor chips includes a second adhesive film. The method includes compressing the first and second adhesive films to form an adhesive structure. The adhesive structure includes an extension disposed on sidewalls of the first and second semiconductor chips. The method includes removing the extension. The method includes forming a first molding layer substantially covering the first and second semiconductor chips. The method includes performing a cutting process on the package substrate between the first and second semiconductor chips to form a plurality of semiconductor packages each including at least one of the first semiconductor chips and at least one of the second semiconductor chips.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: February 16, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Won-Gi Chang, Dongwon Lee, Myung-Sung Kang, Hyein Yoo
  • Publication number: 20190273075
    Abstract: A method for manufacturing a semiconductor device includes stacking, on a package substrate, first semiconductor chips. Each of the first semiconductor chips includes a first adhesive film. The method includes stacking, respectively on the first semiconductor chips, second semiconductor chips. Each of the second semiconductor chips includes a second adhesive film. The method includes compressing the first and second adhesive films to form an adhesive structure. The adhesive structure includes an extension disposed on sidewalls of the first and second semiconductor chips. The method includes removing the extension. The method includes forming a first molding layer substantially covering the first and second semiconductor chips. The method includes performing a cutting process on the package substrate between the first and second semiconductor chips to form a plurality of semiconductor packages each including at least one of the first semiconductor chips and at least one of the second semiconductor chips.
    Type: Application
    Filed: May 21, 2019
    Publication date: September 5, 2019
    Inventors: Won-Gi Chang, Dongwon Lee, Myung-Sung Kang, Hyein Yoo
  • Patent number: 10354985
    Abstract: A method for manufacturing a semiconductor device includes stacking, on a package substrate, first semiconductor chips. Each of the first semiconductor chips includes a first adhesive film. The method includes stacking, respectively on the first semiconductor chips, second semiconductor chips. Each of the second semiconductor chips includes a second adhesive film. The method includes compressing the first and second adhesive films to form an adhesive structure. The adhesive structure includes an extension disposed on sidewalls of the first and second semiconductor chips. The method includes removing the extension. The method includes forming a first molding layer substantially covering the first and second semiconductor chips. The method includes performing a cutting process on the package substrate between the first and second semiconductor chips to form a plurality of semiconductor packages each including at least one of the first semiconductor chips and at least one of the second semiconductor chips.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: July 16, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Won-Gi Chang, Dongwon Lee, Myung-Sung Kang, Hyein Yoo
  • Patent number: 10115613
    Abstract: The present disclosure relates to a method of fabricating a semiconductor package. The method may include forming a cavity in a package substrate and providing the package substrate and a die on a carrier tape film. Here, the carrier tape film may include a tape substrate and an insulating layer on the tape substrate, and the die may be provided in the cavity of the package substrate. The method may further include subsequently forming an encapsulation layer to cover the insulating layer and the die in the cavity and cover the package substrate on the insulating layer and removing the tape substrate from the insulating layer.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: October 30, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Won-Gi Chang, Yeongseok Kim, Hyein Yoo
  • Publication number: 20170365591
    Abstract: A method for manufacturing a semiconductor device includes stacking, on a package substrate, first semiconductor chips. Each of the first semiconductor chips includes a first adhesive film. The method includes stacking, respectively on the first semiconductor chips, second semiconductor chips. Each of the second semiconductor chips includes a second adhesive film. The method includes compressing the first and second adhesive films to form an adhesive structure. The adhesive structure includes an extension disposed on sidewalls of the first and second semiconductor chips. The method includes removing the extension. The method includes forming a first molding layer substantially covering the first and second semiconductor chips. The method includes performing a cutting process on the package substrate between the first and second semiconductor chips to form a plurality of semiconductor packages each including at least one of the first semiconductor chips and at least one of the second semiconductor chips.
    Type: Application
    Filed: February 21, 2017
    Publication date: December 21, 2017
    Inventors: WON-GI CHANG, DONGWON LEE, MYUNG-SUNG KANG, HYEIN YOO
  • Publication number: 20170358535
    Abstract: Provided are a semiconductor package. The semiconductor package comprises a redistribution substrate, an interconnect substrate on the redistribution substrate and including a hole penetrating therethrough and a recess region in a lower portion thereof, a semiconductor chip on the redistribution substrate and disposed in the hole of the interconnect substrate, and a molding layer covering the semiconductor chip and the interconnect substrate. The recess region is connected to the hole. The mold layer fills the recess region and a gap between the semiconductor chip and the interconnect substrate.
    Type: Application
    Filed: June 8, 2017
    Publication date: December 14, 2017
    Inventors: Hyein YOO, Won-Gi CHANG
  • Publication number: 20170358467
    Abstract: The present disclosure relates to a method of fabricating a semiconductor package. The method may include forming a cavity in a package substrate and providing the package substrate and a die on a carrier tape film. Here, the carrier tape film may include a tape substrate and an insulating layer on the tape substrate, and the die may be provided in the cavity of the package substrate. The method may further include subsequently forming an encapsulation layer to cover the insulating layer and the die in the cavity and cover the package substrate on the insulating layer and removing the tape substrate from the insulating layer.
    Type: Application
    Filed: March 27, 2017
    Publication date: December 14, 2017
    Inventors: Won-Gi CHANG, YEONGSEOK KIM, Hyein YOO
  • Patent number: 8338962
    Abstract: A semiconductor package may include a package substrate having a first surface and a boundary that may be defined by edges of the package substrate. The package further includes a first semiconductor chip having a front surface and a back surface. The back surface of a first portion of the first semiconductor chip may be disposed on the first surface of the package substrate with the back surface of a second portion of the first semiconductor chip extending beyond of the defined boundary of the package substrate. The semiconductor package may also include a second semiconductor chip disposed on the back surface of the second portion of the first semiconductor chip that extends beyond the defined boundary of the package substrate.
    Type: Grant
    Filed: March 27, 2011
    Date of Patent: December 25, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-gi Chang, Tae-sung Park
  • Publication number: 20120038035
    Abstract: A semiconductor package may include a package substrate having a first surface and a boundary that may be defined by edges of the package substrate. The package further includes a first semiconductor chip having a front surface and a back surface. The back surface of a first portion of the first semiconductor chip may be disposed on the first surface of the package substrate with the back surface of a second portion of the first semiconductor chip extending beyond of the defined boundary of the package substrate. The semiconductor package may also include a second semiconductor chip disposed on the back surface of the second portion of the first semiconductor chip that extends beyond the defined boundary of the package substrate.
    Type: Application
    Filed: March 27, 2011
    Publication date: February 16, 2012
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Won-gi Chang, Tae-sung Park