Abstract: Disclosed is a high voltage output device having a serial-parallel stack structure of capacitors. The high voltage output device includes a substrate includes a capacitor element and a pillar structure provided on an upper surface of the substrate. The substrate includes a first electrode and a second electrode, which have different potentials from each other. The capacitor element is connected to at least one of the first electrode and the second electrode.

Abstract: A low-density parity check (LDPC) code decoding method may be provided. The LDPC code decoding method may linearize or perform step-approximation on a natural logarithm hyperbolic cosine function included in a check node updating equation of a sum-product algorithm used for decoding an LDPC code, and may convert the linearized function to correspond to a check node updating equation of a min-sum algorithm.

Abstract: Provided are an apparatus for addition data transmission includes: an IF broadcasting signal generating unit receiving the broadcast data, and FEC and modulation of the received broadcast data to generate a broadcasting signal in an intermediate frequency (IF) band; an IF addition signal generating unit receiving the addition data to generate an addition signal in the IF band by using direct sequence spread spectrum (DSSS); an average power controlling unit controlling average power of the addition signal in the IF band; a signal combining unit combining the broadcasting signal in the IF band and the addition signal in the IF band to generate a combination signal; an RF upward converting unit upwardly converting the combination signal in a signal in a radio frequency (RF) band to a combination signal in the RF band; and a transmitting unit transmitting the combination signal in the RF band.

Abstract: A broadband wireless system includes an antenna receiving a broadband wireless signal, a reception unit receiving and processing the broadband wireless signal from the antenna and converting the broadband wireless signal into a first intermediate frequency signal, a signal distribution unit converting a first intermediate frequency signal into second intermediate frequency signals which are equal to one another, a parallel amplification unit generating third intermediate frequency signals which are obtained by amplifying the individual second intermediate frequency signals provided from the signal distribution unit with different amplification rates, a parallel analog-to-digital conversion unit performing analog-to-digital conversion of the individual third intermediate frequency signals from the parallel amplification unit and generating discrete intermediate frequency signals, and an execution system selecting any one of the individual discrete intermediate frequency signals by analyzing the individual disc

Abstract: A low-density parity check (LDPC) code decoding method may be provided. The LDPC code decoding method may linearize or perform step-approximation on a natural logarithm hyperbolic cosine function included in a check node updating equation of a sum-product algorithm used for decoding an LDPC code, and may convert the linearized function to correspond to a check node updating equation of a min-sum algorithm.

Abstract: Disclosed is a broadband wireless system which has a high bit resolution and a wide operating range, enables measurement and use of signal specifications such as an arrival time, strength, frequency, pulse width, modulation type of a signal, has a simple configuration with high reliability, and enables easy use of the processed signal.