Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, an active pattern extending in a first horizontal direction on the substrate, a gate electrode extending in a second horizontal direction different from the first horizontal direction on the active pattern, a source/drain region on at least one side of the gate electrode, a source/drain contact extending into the source/drain region and including a filling layer and a barrier layer along a sidewall of the filling layer, and a silicide layer between the source/drain region and the filling layer, the silicide layer including a first sidewall in contact with the filling layer and a second sidewall in contact with the source/drain region, wherein the barrier layer is not between the filling layer and the source/drain region.

Abstract: Provided is a semiconductor device. The semiconductor device comprises a first active pattern extending in a first direction on a substrate, a second active pattern which extends in the first direction and is adjacent to the first active pattern in a second direction different from the first direction, a field insulating film placed between the first active pattern and the second active pattern, a first gate structure which crosses the first active pattern, extends in the second direction, and includes a first gate electrode and a first gate spacer, a second gate structure which crosses the second active pattern, extends in the second direction, and includes a second gate electrode and a second gate spacer, a gate separation structure placed on the field insulating film between the first gate structure and the second gate structure.

Abstract: A semiconductor device includes a substrate with first and second regions separated from each other, a laminate structure including at least one sacrificial layer and at least one active layer alternately stacked on the substrate, a first isolation insulating layer on the laminate structure on the first region, a second isolation insulating layer on the laminate structure on the second region, the second isolation insulating layer having a same thickness as the first isolation insulating layer, a first upper active pattern spaced apart from the first isolation insulating layer, a first gate electrode surrounding at least a portion of the first upper active pattern, a second upper active pattern spaced apart from the second isolation insulating layer, and a second gate electrode surrounding at least a portion of the second upper active pattern, wherein top surfaces of the first and second isolation insulating layers are at different heights.

Abstract: The present invention relates to a radiant tube apparatus disposed in a heat treatment facility to perform a heat treatment of a strip and a method for manufacturing the same. The radiant tube apparatus includes a tube having an internal pipe, wherein the tube has a first continuous pattern and a second continuous pattern extending side by side and spaced apart from each other at a predetermined distance on a surface, and, in each of the first continuous pattern and the second continuous pattern, a plurality of unit patterns having a predetermined height from the surface are connected to each other in a longitudinal direction.

Abstract: Proposed is a thermoelement heat exchange module including a body and a thermoelement. The body has a cooling water flow path through which cooling water flows and has an opening which communicates with the cooling water flow path, and has an inlet which is formed at a first side thereof to communicate with the cooling water flow path and through which cooling water is introduced and has an outlet which is formed at a second side thereof to communicate with the cooling water flow path and through which cooling water is discharged. The thermoelement has a first surface thereof coupled to a portion where the opening of the body is formed such that the first surface is exposed on the cooling water flow path. The cooling water flow path has a portion having a relatively small hydraulic diameter in a flow direction of cooling water.

Abstract: A semiconductor device includes a substrate with first and second regions separated from each other, a laminate structure including at least one sacrificial layer and at least one active layer alternately stacked on the substrate, a first isolation insulating layer on the laminate structure on the first region, a second isolation insulating layer on the laminate structure on the second region, the second isolation insulating layer having a same thickness as the first isolation insulating layer, a first upper active pattern spaced apart from the first isolation insulating layer, a first gate electrode surrounding at least a portion of the first upper active pattern, a second upper active pattern spaced apart from the second isolation insulating layer, and a second gate electrode surrounding at least a portion of the second upper active pattern, wherein top surfaces of the first and second isolation insulating layers are at different heights.

Abstract: A semiconductor device including a device isolation region is provided. The semiconductor device includes first active regions disposed on a substrate, and an isolation region between the active regions. The isolation region includes a first portion formed of a first insulating material, and a second portion formed of a second insulating material, having different characteristics from those of the first insulating material. The first portion is closer to the first active regions than the second portion. The second portion has a bottom surface having a height different from that of a bottom surface of the first portion.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, an active pattern extending in a first horizontal direction on the substrate, a gate electrode extending in a second horizontal direction different from the first horizontal direction on the active pattern, a source/drain region on at least one side of the gate electrode, a source/drain contact extending into the source/drain region and including a filling layer and a barrier layer along a sidewall of the filling layer, and a silicide layer between the source/drain region and the filling layer, the silicide layer including a first sidewall in contact with the filling layer and a second sidewall in contact with the source/drain region, wherein the barrier layer is not between the filling layer and the source/drain region.

Abstract: In some aspects, the present disclosure provides a method for identifying one or more biomolecules. In some embodiments, the method comprises generating a set of biomolecules by incubating a cell in a supplemented medium under conditions sufficient for the cell to generate the set of biomolecules. In some embodiments, the method comprises contacting at least a portion of the supplemented medium with one or more surfaces to adsorb the set of biomolecules. In some embodiments, the method comprises removing the one or more surfaces and the set of biomolecules from the at least the portion of the supplemented medium to produce a separated sample. In some embodiments, the method comprises releasing, in the separated sample, the set of biomolecules from the one or more surfaces. In some embodiments, the method comprises detecting at least a subset of the set of biomolecules, thereby identifying one or more biomolecules.

Abstract: A stator assembly is provided and includes a stator element and a radial height adjustment mechanism. The stator assembly includes an inboard portion which establishes a primary clearance with rotor elements and exhibits a measurable parameter corresponding to the primary clearance and an outboard portion integrally formed with the inboard portion. The radial height adjustment mechanism is coupled with the outboard portion and configured to be operable, based on the measurable parameter, to adjust a radial height of the stator element and in turn to adjust the primary clearance.

Abstract: A stator cluster is provided and includes inner and outer stator walls, stator vanes radially interposed between the inner and outer stator walls and a stanchion body connected to and extending radially outwardly from the outer stator wall. At least the stator vanes, the outer stator wall and the stanchion body are formed to define internal paths.

Abstract: There is provided a semiconductor device manufactured using a method that reduces a manufacturing time and cost of the semiconductor device. The semiconductor device includes a first semiconductor device module including: a first lower bonding pad; a second lower bonding pad; first upper bonding pads; and a memory cell disposed at a height level higher than a height level of each of the first and second lower bonding pads and lower than a height level of the first upper bonding pads. The semiconductor device further comprises a second semiconductor device module including second bonding pads and a transistor electrically connected to at least one of the second bonding pads; and a third semiconductor device module including third bonding pads. The third pads are spaced apart from the first and second lower bonding pads in a first direction. The first lower bonding pad contacts at least one of the second bonding pads. At least one of the third bonding pads contacts at least one of the first upper bonding pads.

Abstract: A stator cluster is provided and includes inner and outer stator walls, stator vanes radially interposed between the inner and outer stator walls and a stanchion body connected to and extending radially outwardly from the outer stator wall. At least the stator vanes, the outer stator wall and the stanchion body are formed to define internal paths.

Abstract: Provided is a semiconductor device. The semiconductor device comprises a first active pattern extending in a first direction on a substrate, a second active pattern which extends in the first direction and is adjacent to the first active pattern in a second direction different from the first direction, a field insulating film placed between the first active pattern and the second active pattern, a first gate structure which crosses the first active pattern, extends in the second direction, and includes a first gate electrode and a first gate spacer, a second gate structure which crosses the second active pattern, extends in the second direction, and includes a second gate electrode and a second gate spacer, a gate separation structure placed on the field insulating film between the first gate structure and the second gate structure.

Abstract: A heat controllable battery pack is provided. The battery pack includes a lower cover including a first cooling line, through which a refrigerant moves, installed therein and supporting a lower portion of a plurality of cell modules, a plurality of crash structures installed in positions between the plurality of cell modules on an upper portion of the lower cover and including a second cooling line, through which the refrigerant cooling the cell modules moves, installed therein, a side frame protecting side surfaces of the plurality of cell modules, and an upper cover covering an upper portion of the plurality of cell modules.

Abstract: A multi-bio-signal-based geriatric cognitive impairment diagnosis method includes collecting multiple bio-signals including brain waves, heart rate variability, and gait measurement values of a subject during walking; calculating a probability value of a geriatric cognitive impairment disease by using a cognitive impairment diagnosis model, based on the multiple bio-signals; and determining whether there is a geriatric cognitive impairment disease, based on a calculated probability value, wherein the cognitive impairment diagnosis model is a model constructed by applying brain waves, heart rate variability, and gait measurement values of a patient with a geriatric cognitive impairment disease to a logistic function.

Abstract: A semiconductor device including: a lower semiconductor substrate; an upper semiconductor substrate overlapping the lower semiconductor substrate, the upper semiconductor substrate including a first surface and a second surface opposite to the first surface; an upper gate structure on the first surface of the upper semiconductor substrate; a first interlayer insulation film which covers the upper gate structure, wherein the first interlayer insulation film is between the lower semiconductor substrate and the upper semiconductor substrate; and an upper contact connected to the lower semiconductor substrate, wherein the upper contact is on a side surface of the upper gate structure, wherein the upper contact includes a first portion penetrating the upper semiconductor substrate, and a second portion having a side surface adjacent to the side surface of the upper gate structure, and a width of the first portion decreases toward the second surface.

Abstract: According to the organometallic compound of the present invention and the thin film manufactured using the same, requirements of high volatility and excellent chemical/thermal stability are satisfied, and significantly improved thin-film deposition rates are exhibited even at low temperatures. In addition, property degradation due to by-products can be improved, excellent step coverage can be realized, and a thin film which, due to having a high dielectric constant, electrically satisfies the equivalent oxide thickness (EOT) requirement while having a thickness at which tunneling does not physically occur can be implemented.

Abstract: There is provided a semiconductor memory device comprising: a first word line; a second word line spaced apart from the first word line, a back gate electrode between the first word line and the second word line; a first channel pattern between the first word line and the back gate electrode; a second channel pattern between the second word line and the back gate electrode; a first gate insulating film between the first word line and the first channel pattern; a second gate insulating film between the second word line and the second channel pattern; a first bit line on the first channel pattern and the second channel pattern, wherein the first bit line is connected to the first channel pattern; and a second bit line on the first channel pattern and the second channel pattern, wherein the second bit line is connected to the second channel pattern.

Abstract: A method of manufacturing a semiconductor device, the method including providing a substrate including a first region and a second region such that the second region is separated from the first region; forming a metal oxide film on the first region of the substrate and the second region of the substrate; forming an upper metal material film on the metal oxide film on the first region of the substrate such that the upper metal material film does not overlap the metal oxide film on the second region of the substrate; and simultaneously annealing the upper metal material film and the metal oxide film to form a ferroelectric insulating film on the first region of the substrate and form a paraelectric insulating film on the second region of the substrate.